VERILOG HDL
Special classes
Chapter1
Basic concepts of VLSI circuits
1 list merits of cmos technology ?
High input impedence
The outputs actively drive both ways
The outputs are pretty much rail to rail
CMOS logic take very little power when held on a fixed
state
Cmos gates are very simple
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Chapter 2
Design flow for designing VLSI IC
cateory
User defined data types VHDL
Multi dimensional arrays Available Verilog HDL
Librares or packages Can be used Not available
Easy to learn Are used Can not be used
Predefined unary Rigd,hard to learn Not used
operator No Easy to learn
Code simplified by using Procedures Yes
tasks
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2.List importantc features of verilog HDL
Verilog HDL is a general purpose HDL that is easy to use
and learn
It is similar in syntax with c programming language
Verilog HDL allows different levels of abstraction and
mixed them
Most popular logical sysnthesis support verilog HDL.this
makes it the language of choice for designers
All fabrication venders provide verilog HDL libraries for
post logic synthesis simulation.thus ,designing a chip in
verilog HDL allows the widest choice of vendors.
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3.Explain the difference between an
instantiation and inference ?
1.Instantiation:when u instantiate a component , you add an instance of that component
to your HDL file or schematic . vendor provides the following methods for instantiating
components:
Hdl : in an HDL File , you must use specific syntax to instantiate a component . for your
convinence , the ISE software provides language templetes ,which are pre built code
examples that you can create and store your own user templetes.
Schematic:in a schematic file,you can instantiate components from the vendor unified
library provided with the ISE software . you can also create your own schematic symbols
to instantiate.
2.inference:when you infer a component ,you provide a description of the function you want
to accomplish . The synthesis tool then interprets the HDL code to determine which
hardware components to use to perform the function . For your convenience , the ISE
software provides language templetes , which are pre build code examples that you can
insert into your own design file . You can also store your own user templetes .
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4.Explain differences between modules and module
instances in verilog
Module :A module is a basic building in verilog . A module
can be an element or a collection of lower-level design blocks
. Typically , elemnts are grouped into modules to provide
common functionality that is used at many places in design.
Module instantiation : a module provides a template from
which you can create actual objects . When a module is
invoked , verilog creates a unique object from the templete .
Each object has its own name , variables , parameters and
I/O interface . The process of creating module from module
template is called instantiation , the objects are called
instances .
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5.Identify the components of verilog module definition ?
Module name ,
Port list , port declaration(if ports present)
Parameters(optional),
Declarations of wires , reg Data flow
and other variables statements(assign)
Instantiation of lower level Always and initial blocks.
modules All behavioural statements
go in these blocks.
tasks and functions
Endmodule statement
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6.Define expressions , operators and operands ?
Expressions : expressions are constructs that combine
operators and operands to produce a result .
//examples of expressions . Combines operators and
operands
a^b ,
addr 1 [20:17] + addr2[20:17]
In1 | in2
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Operands : operands can be any one of data types .
Some constructs will take only certain types of
operands . Operands can be integers , constants , real
numbers , nets , registers , times , bit select , part-
select , and memories or function calls .
Examples:
Real a , b , c;
c = a – b ; // a and b are real operands
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Operators : operators act on the operands to produce
desired results . Some of operators are logical
operator , arithmetic operator , bit-wise operator .
D1 && d2 //&& is a operator on operands d1 and d2
!a[0] //! Is a operator on a[0]
B >> 1 //>> is a operator on operands b and 1
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Thank you
DECE
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