§3.
4 Division
Division
Check for 0 divisor
Long division approach
quotient If divisor ≤ dividend bits
dividend 1 bit in quotient, subtract
1001 Otherwise
1000 1001010 0 bit in quotient, bring down next
-1000 dividend bit
divisor
10 Restoring division
101 Do the subtract, and if remainder
1010 goes < 0, add divisor back
-1000 Signed division
remainder 10 Divide using absolute values
Adjust sign of quotient and remainder
n-bit operands yield n-bit as required
quotient and remainder
Division Hardware
Initially divisor
in left half
Initially dividend
Optimized Divider
Dividend initially
Remainder, Quotient
One cycle per partial-remainder subtraction
Looks a lot like a multiplier!
Same hardware can be used for both
Faster Division
Can’t use parallel hardware as in multiplier
Subtraction is conditional on sign of remainder
Faster dividers (e.g. SRT devision)
generate multiple quotient bits per step
Still require multiple steps
MIPS Division
Use HI/LO registers for result
HI: 32-bit remainder
LO: 32-bit quotient
Instructions
div rs, rt / divu rs, rt
No overflow or divide-by-0 checking
Software must perform checks if required
Use mfhi, mflo to access result
Floating Point
Representation for non-integral numbers
Including very small and very large numbers
Like scientific notation
–2.34 × 1056 normalized
+0.002 × 10–4 not normalized
+987.02 × 109
In binary
±1.xxxxxxx2 × 2yyyy
Types float and double in C
Floating Point Standard
Defined by IEEE Std 754-1985
Developed in response to divergence of
representations
Portability issues for scientific code
Now almost universally adopted
Two representations
Single precision (32-bit)
Double precision (64-bit)
IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction
x ( 1)S (1 Fraction) 2(ExponentBias) View + as
a binary
S: sign bit (0 non-negative, 1 negative) point .
Normalize significand: 1.0 ≤ |significand| < 2.0
Always has a leading pre-binary-point 1 bit, so no need to
represent it explicitly (hidden bit)
Significand is Fraction with the “1.” restored
Exponent: excess representation: actual exponent + Bias
Ensures exponent is unsigned
Single: Bias = 127; Double: Bias = 1203
Single-Precision Range
Exponents 00000000 and 11111111 reserved
Smallest value
Exponent: 00000001
actual exponent = 1 – 127 = –126
Fraction: 000…00 significand = 1.0
±1.0 × 2–126 ≈ ±1.2 × 10–38
Largest value
exponent: 11111110
actual exponent = 254 – 127 = +127
Fraction: 111…11 significand ≈ 2.0
±2.0 × 2+127 ≈ ±3.4 × 10+38
Double-Precision Range
Exponents 0000…00 and 1111…11 reserved
Smallest value
Exponent: 00000000001
actual exponent = 1 – 1023 = –1022
Fraction: 000…00 significand = 1.0
±1.0 × 2–1022 ≈ ±2.2 × 10–308
Largest value
Exponent: 11111111110
actual exponent = 2046 – 1023 = +1023
Fraction: 111…11 significand ≈ 2.0
±2.0 × 2+1023 ≈ ±1.8 × 10+308
Floating-Point Example
Represent –0.75
–0.75 = (–1)1 × 1.12 × 2–1
S=1
Fraction = 1000…002
Exponent = –1 + Bias
Single: –1 + 127 = 126 = 011111102
Double: –1 + 1023 = 1022 = 011111111102
Single: 1 01111110 1000…00
Double: 1 01111111110 1000…00
Floating-Point Example
What number is represented by the single-
precision float
1 10000001 01000…00
S=1
Fraction = 01000…002
Fxponent = 100000012 = 129
x = (–1)1 × (1 + 012) × 2(129 – 127)
= (–1) × 1.25 × 22
= –5.0
Floating-Point Addition
1. Align decimal points
Shift number with smaller exponent
2. Add significands
3. Normalize result & check for over/underflow
4. Round and renormalize if necessary
Floating-Point Addition
Consider a 4-digit decimal example
9.999 × 101 + 1.610 × 10–1
1. Align decimal points
Shift number with smaller exponent
9.999 × 101 + 0.016 × 101
2. Add significands
9.999 × 101 + 0.016 × 101 = 10.015 × 101
3. Normalize result & check for over/underflow
1.0015 × 102
4. Round and renormalize if necessary
1.002 × 102
Floating-Point Addition
Now consider a 4-digit binary example
1.0002 × 2–1 + –1.1102 × 2–2 (in decimal 0.5 + –0.4375)
1. Align binary points
Shift number with smaller exponent
1.0002 × 2–1 + –0.1112 × 2–1
2. Add significands
1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1
3. Normalize result & check for over/underflow
1.0002 × 2–4, with no over/underflow
4. Round and renormalize if necessary
1.0002 × 2–4 (no change) = 0.0625
FP Adder Hardware
Much more complex than integer adder
Doing it in one clock cycle would take too
long
Much longer than integer operations
Slower clock would penalize all instructions
FP adder usually takes several cycles
Can be pipelined
FP Adder Hardware
Step 1
Step 2
Step 3
Step 4
Floating-Point Multiplication
1. Add exponents
For biased exponents, subtract bias from sum
2. Multiply significands
3. Normalize result & check for over/underflow
4. Round and renormalize if necessary
5. Determine sign of result from signs of operands
Floating-Point Multiplication
Consider a 4-digit decimal example
1.110 × 1010 × 9.200 × 10–5
1. Add exponents
For biased exponents, subtract bias from sum
New exponent = 10 + –5 = 5
2. Multiply significands
1.110 × 9.200 = 10.212 10.212 × 105
3. Normalize result & check for over/underflow
1.0212 × 106
4. Round and renormalize if necessary
1.021 × 106
5. Determine sign of result from signs of operands
+1.021 × 106
Floating-Point Multiplication
Now consider a 4-digit binary example
1.0002 × 2–1 × –1.1102 × 2–2 (in decimal 0.5 × –0.4375)
1. Add exponents
Unbiased: –1 + –2 = –3
Biased: (–1 + 127) + (–2 + 127) = –3 + 254 – 127 = –3 + 127
2. Multiply significands
1.0002 × 1.1102 = 1.1102 1.1102 × 2–3
3. Normalize result & check for over/underflow
1.1102 × 2–3 (no change) with no over/underflow
4. Round and renormalize if necessary
1.1102 × 2–3 (no change)
5. Determine sign: +ve × –ve –ve
–1.1102 × 2–3 = –0.21875
FP Arithmetic Hardware
FP multiplier is of similar complexity to FP
adder
But uses a multiplier for significands instead of
an adder
FP arithmetic hardware usually does
Addition, subtraction, multiplication, division,
reciprocal, square-root
FP integer conversion
Operations usually takes several cycles
Can be pipelined
Accurate Arithmetic
IEEE Std 754 specifies additional rounding
control
Extra bits of precision (guard, round, sticky)
Choice of rounding modes
Allows programmer to fine-tune numerical behavior of
a computation
Not all FP units implement all options
Most programming languages and FP libraries just
use defaults
Trade-off between hardware complexity,
performance, and market requirements
Subword Parallellism
Graphics and audio applications can take
advantage of performing simultaneous
operations on short vectors
Example: 128-bit adder:
Sixteen 8-bit adds
Eight 16-bit adds
Four 32-bit adds
Also called data-level parallelism, vector
parallelism, or Single Instruction, Multiple
Data (SIMD)
Associativity
Parallel programs may interleave
operations in unexpected orders
Assumptions of associativity may fail
(x+y)+z x+(y+z)
x -1.50E+38 -1.50E+38
y 1.50E+38 0.00E+00
z 1.0 1.0 1.50E+38
1.00E+00 0.00E+00
Need to validate parallel programs under
varying degrees of parallelism
