TEST

1. Fundamentals of Microelectronics
2. ASICs design
3. Static Timing Analysis
4. Introduction to library formats
Vo Thi Phuong Chi
FUNDAMENTALS OF
MICROELECTRONICS
 ▸When logic 1 is applied as input, NMOS transistor turns ON and PMOS

1
transistor turns OFF. At that point, NMOS pulls up the output voltage to logic
1. We have the equation Vgs = Vg – Vs = Vin – Vout, or Vout = Vin – Vgs. We also

have the saturation region of NMOS operation as V gs > Vth. In order for Vout to

get pulled up to the point where it equals to V in, the value of Vgs has to be 0.
Why CMOS However, when Vgs gets to where Vgs < Vth, NMOS has already reached cut off
structure
region. Hence, the output voltage only gets pulled up to the point where V out =
always pull-up
Vin – Vth.
PMOS and
pull-down ▸When logic 0 is applied as input, NMOS transistor turns OFF and PMOS

NMOS, not transistor turns ON. For this reason, the output voltage must be pulled down
to logic 0 by PMOS. We have the saturation region of PMOS operation as V sg
reverse?
> |Vth| (Vth < 0), or Vout – Vin > |Vth|, which leads to Vout > |Vth| + Vin. Because Vth is

always present regardless of Vin getting pulled up to logic 0, Vout will always
2
1. Net delay:
▸ Net delay (wire delay) is the difference between the time a signal
is first applied to the net and the time it reaches other devices
connected to that net.
▸ There are some factors which affect net parasitic:
What factor • Net Length
affect to cell • Net cross-sectional area
and net delay? • Resistively of material used for metal layers (Aluminum vs.
copper)
• Number of vias traversed by the net
• Proximity to other nets (crosstalk)
 2. Cell delay:

2 ▸ CMOS transistors inside a standard cell takes finite amount of

time to switch from one logic state to another. This time taken is
called as the cell delay or the propagation delay of a cell which is
typically specified in the cell timing library (.lib).

What factor
affect to cell
and net delay?
2
▸ There are 3 factors which affect propagation delay:

• Input Slew: The transition time at the input i.e. the time it
takes for an input pin (input capacitance) to switch between
logic states (low-high or high-low). Net cross-sectional area

What factor • Output Capacitance: The capacitance that needs to get

affect to cell charged/discharged at the output of a cell driving single or

multiple loads. This capacitance introduces a finite amount of
and net delay?
delay.

• Intrinsic Delay: The internal delay of a cell when a signal with

zero transition time is applied to the input pin and no output
load is present.
 LEAKAGE POWER: the power consumed by the sub

3
▸
threshold currents and by reverse biased diodes in a CMOS
transistor.

What is leakage Pleakage = VDD Ileakage

power?
(definition, how
it happend,
formula, what
factor affect to
leakage power)
3
LEAKAGE CURRENT MECHANISMS:
• Leakage current is dominated by subthreshold leakage, gate-oxide
tunneling leakage and reverse-bias pn-junction leakage.

• There are still other leakage components, like gate induced drain
What is leakage
leakage (GIDL) and punch through current, however those ones
power?
can be still neglected in normal operation of digital circuits.
(definition, how
it happend,
formula, what
factor affect to
leakage power)
 a. Subthreshold Current:

3
• It is the current between the source and drain of a MOSFET when
the transistor is in subthreshold region, or weak-inversion region,
that is, for gate-to-source voltages below the threshold voltage.

What is leakage
power?
(definition, how Wµ0Cox VT 2e1.8
it happend,  o I0 = L
o VT = is the thermal voltage
formula, what
o Vth : the threshold voltage
factor affect to o Vds and Vgs : the drain-to-source and gate-to-source voltage respectively.
leakage power) o W and L: the effective transistor width and length, respectively.
o Cox : the gate oxide capacitance
o µ0 : the carrier mobility
o n : the subthreshold swing coefficient.
 b. Gate Oxide Tunneling Current:

3
• The tunneling of electrons (or holes) from the bulk and source/drain
overlap region through the gate oxide potential barrier into the gate
(or vice-versa) is referred as gate oxide tunneling current.
• Gate leakage current increases exponentially with decreasing oxide
thickness.

What is leakage
power?
(definition, how
it happend,
o
  W and L : the effective transitor width and length
formula, what o A = q3/16π2hφox
factor affect to o b = 4π 2m φoxox /3hq
3/2

leakage power) o mox : the effectice mass of the tunneling particle

o φox : the tunneling barrier height
o tox : the oxide thickness
o h : 1/2 π times Planck’s constant
 c. Reverse-bias pn-junction leakage:

3 • The MOS transistor has two pn junctions – drain and source to well junctions.
These junctions are typically reverse biased, causing a pn junction leakage
current. This current is a function of junction area and doping concentration.
When ‘n’ and ‘p’ regions are heavily doped, band-to-band tunneling (BTBT)
What is leakage leakage dominates the reverse biased pn junction leakage mechanism.
power? • A high electric field across a reverse biased pn junction causes a current flow
(definition, how through the junction due to tunneling of electrons from the valence band of
it happend, the p-region to the conduction band of the n-region.
formula, what
factor affect to
leakage power)
3  
What is leakage o A = 4π2m*q3 / 4π3h2
power? o B = 4π2m*q3 /3hq
(definition, how o m* : the effective mass of electron
it happend, o Eg : the energy-band gap
formula, what o Vapp : the applied reverse bias
factor affect to o E : the electric field at the junction
leakage power)
o q : the electron charge
o h : 1/2 π times the Planck’s constant
3
Factors affect to leakage power:
▸ Leakage power of a CMOS transistor depends on gate length and oxide
layer thickness

▸ Subthreshold leakage increases exponentially with decrease in Vth and

What is leakage
increase in temperature. It can also be strongly dependent on transistor
power?
channel length in short channel devices.
(definition, how
▸ Gate leakage has increased exponentially with reduction in gate oxide
it happend,
thickness.
formula, what
▸ The pn junction reverse-biased leakage current depends on doping
factor affect to
concentration and junction area.
leakage power)
ASICs DESIGN
4 Standard Cell Utilization:
▸ It is defined as the ratio of the area of the standard
Cells to the area of the chip minus the area of the
What is
macros and area of blockages.
Standard cell
utilization? ▸ %U = (std cell area) / (core area – [macro area +
blockage area])
 a. WHAT IS ROUTING CONGESTION?

5
▸ Routing congestion occurs when too many routes need to go through an area
that does not have enough resources - or “routing tracks” - to accommodate
them.

b. WHAT CAUSES CONGESTION?

▸ Global Congestion: This occurs when there are a lot of chip-level or inter-block
What is routing wires that need to cross an area.
congestion? ▸ Local Congestion (Floorplan congestion): This occurs when the floorplan has
How to improve macros and other routing blockages that are too close together to get enough
routing routes through to connect to the macros.
congestion? ▹ Placement density congestion: Placement utilization is basically how
densely the cells are placed.
▹ Logic-induced congestion: Logic structure and cell selection can create
congestion.
5 Logic-induced congestion

What is routing
congestion?
How to improve
routing Floorplan-induced congestion

congestion?
5
c. HOW TO IMPROVE ROUTING CONGESTION?
▸ Modify floorplaning (moving macros, creating more space around
the macros, creating placement blockages, rearranging the macro
placement or orientation, change core shape/size...).

▸ Move pins to give enough room for routing.

What is routing
▸ Use/Modify proper blockages (i.e., Soft blockages, Hard blockages,
congestion?
How to improve Macro Padding) are used proper locations to minimize the

routing congestion near macros.

congestion? ▸ Modify physical constraints such as adjust cell density in

congested areas (Higher cell density cause for congestion).
6
What are the steps in Physical design flow and explain each step?

PHYSICAL
FLOORPLAN PLACEMENT CTS ROUTING CHIP FINISH STA
VERIFICATION
6 FLOORPLAN
 The floorplanning problem is performing a
floorplan-level placement of macros at the
beginning of the design.
 Major task:  Goal:
• Chip Size decision • Miniminal chip size
• I/O pad arrangement • Routable
• Macro arrangement • Good for timing optimization
• Module placement guidance • Strong (enough) Power and Ground
• Power Ground structure creation
6 FLOORPLAN

 Input:  Output:
• Netlist (.v) • Die/Core Area
• Technology file (techlef) • I/O placed
• Timing Library files (.lib) • Macros placed
• Physical library (.lef) • Power Grid designed
• Synopsys design constraints • Standard Cells placement area
(.sdc)
6 FLOORPLAN
 Steps in Floorplan:
• Initialize with Chip & Core Aspect Ratio
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing  Important steps in Floorplan:
• Pins/ Pads Placement • Core boundary
• Macro Placement by Fly-line Analysis • Pins Placement
• Macro Placement • Macro Placement
• Blockage Management (Placement/Routing) • Creating Power Rings and Straps
6 PLACEMENT
 Placement is the process of placing standard cells in
the design. The tool determines the location of each
standard cell on the die.

 Placement does not only just place standard cells available in the synthesized netlist but also
optimizes the design and determines the routability of design.
 Goal:
• Timing, Power and Area Optimization
• Minimum Congestion
• Minimal cell density, pin density and congestion hot-spots
• Minimal timing DRVs
6 PLACEMENT

 Input:  Output:
• Netlist (.v) • Congestion report
• Technology file (techlef) • Timing report
• Timing Library files (.lib) • Logs
• Physical library (.lef) • Placement DEF file
• Synopsys design constraints (.sdc) • Design with all std cells placed in core area
• Floorplan & Powerplan DEF file
 Input information:
Netlist
Mapped and floorplanned design
Logical and physical libraries
Design constraints

Reading Gate-level netlists from synthesis

 Placement steps: Global (coarse) placement

Detailed placement

Placement optimization

Output information:
Physical layout information
Cell placement locations
Physical layout, timing, and technology information of reference libraries
6 CLOCK TREE SYNTHESIS (CTS)

 CTS is the process of distributing clock signals to

clock pins based on physical/layout information.
 After placement of cells the tree of
synchronization is synthesized.
 Balanced clock tree is synchronized with the
addition of buffers.
 After routing CT optimization is made.
6
 Goal:
CLOCK TREE SYNTHESIS (CTS)
• Meeting the clock tree design rule constraints
- Maximum transition delay
- Maximum load capacitance
- Maximum fanout
- Maximum buffer levels
• Meeting the clock tree targets
Constraints are upper bound goals. If
- Minimum skew constraints are not met, violations will
be reported.
- Min insertion delay
6
 Input:
CLOCK TREE SYNTHESIS (CTS)
 Output:
• Netlist (.v) • Congestion report
• Technology file (techlef) • Timing report
• Timing Library files (.lib) • Skew report
• Physical library (.lef) • CTS DEF file
• Synopsys design constraints (.sdc) • Insertion delay report
• Placement DEF file
• Clock specification file which contains
Insertion delay, skew, clock cells, CTS tree
type, list of buffers/inverters…
6 CLOCK TREE SYNTHESIS (CTS)
 Prerequisites for Clock Tree Synthesis:
Before running CTS, the design must meet the following requirements:
• The design should be placed and optimized.
• Placement – completed; Power and ground nets – prerouted.
• Estimated congestion – acceptable.
• Estimated timing – acceptable (~0ns slack).
• Estimated max cap/transition – no violations.
• High fanout nets
- Reset, Scan Enable synthesized with buffers.
- Clocks are still not buffered.
6 CLOCK TREE SYNTHESIS (CTS)
1. Clock Latency: A delay line is added to meet the minimum insertion delay

2. Clock skew:

• Positive skew

• Negative skew

• Global skew

• Local skew

• Boundary skew

• Useful skew
6 ROUTE

 Routing creates physical connections to all  Goal:

clock and signal pins through metal • Minimizing routing area

interconnects. - Minimizing wiring length
 Routed paths must meet setup and hold timing, - Minimizing channel height
max cap/trans, power and clock skew • Minimizing lengths of critical paths
requirements. • 100% completion in allocated space
- Fixed wiring areas
 Metal traces must meet physical DRC
• Minimizing crosstalk
requirements.
6 ROUTE
 Input:
• Netlist (.v)
• Timing budget for critical nets  Output:
• Locations of blocks and locations of pins • Geometric layouts of all nets

 Objectives:
• Minimizing the total wire length, the number of vias.
• Each net meeting its timing budget.
  Global Routing:

6
• Region definition
• Region assignment
ROUTE • Pin assignment to routing regions
 Track Assignment:
 Routing steps: • Assigns each net to a specific track and
lays down the actual metal traces
• Makes long, straight traces
• Reduces the number of vias

 Detailed Routing:
• Maze
• Line-Probe
• Channel Routing
• Channel vs. Switchbox
• Via / Noise / Shielding…
6 CHIP FINISH

 Chip finish stage comprises 4 basic steps:

• Metal Fill insertion
• Double Via insertion
• Filler cell insertion
• Wire spreading
6 STATIC TIMING ANALYSIS (STA)
 STA is a method to determine if a circuit meets
timing constraints without simulation.
 STA is static since the analysis of the design is
carried out statically and does not depend upon
the data values being applied at the input pins.
 STA is the process in which the delays of a
circuit are calculated by adding the individual
gate and net delays for each path.
6 STATIC TIMING ANALYSIS (STA)
 Input & Output:  Main steps:
• Break the design into sets of
timing paths.
• Calculate the delay of each
path
• Check all path delays to see if
the given timing constraints
are met.
6 STATIC TIMING ANALYSIS (STA)
 Clocks:
• Generated clocks • Clock source latency
• Virtual clocks • Clock network latency
• Gated clocks • Clock skew
• Create clocks • Clock Jitter
• Multiple clocks • Clock uncertainty
- Synchronous clocks
- Asynchronous clocks
- Exclusive clocks
6 STATIC TIMING ANALYSIS (STA)
 Timing Path:
• Data path:
1. in –reg
2. reg – reg
3. reg – out
4. in – out
• Clock path
• Clock gating path
• Asynchronous path
6 STATIC TIMING ANALYSIS (STA)
 Setup time: the minimum amount of time the data signal should be held steady
before the clock event so that the data are reliably sampled.
 Hold time: the minimum amount of time the data signal should be held steady
after the clock event so that the data are reliably sampled.
6 PHYSICAL VERIFICATION
1. Layout vs Schematic (LVS):
 LVS is a verification process to make sure the final netlist (in spice format) matching to the
physical geometry.
 LVS tool takes as an input a schematic diagram and the extracted view (GDS) from a layout. It
generates a netlist (spice) from each one and compares them. Nodes, ports, and device sizing
are all compared. If they are same, LVS passes and designer can continue.
6 PHYSICAL VERIFICATION
2. Design Rule Check (DRC):
 DRC exhaustively compares the physical geometries against a set of “foundry design rules”,
then flags any observed violations. If not follow the rules, any violation of any design rules
would result in a higher probability, and in some cases an absolute certainty that the
fabricated chip does not work as desired.
 Most common rules we need to check:
- Width - Antenna - Bond Pad
- Space - Area - Double Via
- Density - Enclosure
STA
 7
1. Setup time:
Explain about SETUP and HOLD timing?

 Setup time is the interval before the clock where

the data must be held stable.

 Arrival time < Require time

 Slack Setup = Require time – Arrival time

• Slack Setup > 0 : No setup Violation

• Slack Setup < 0 : Setup Violation

 Slack Setup = T + LFF2 – LFF1 – data – Lib – CU ≥ 0

 7 Explain about SETUP and HOLD timing?

 To avoid setup time violations:

• The combinational logic between the flip-flops
should be optimized to get minimum delay.
• Redesign the flip-flops to get lesser setup time.
• Tweak launch flip-flop to have better slew at the
clock pin, this will make launch flip-flop to be
fast there by helping fixing setup violations.
• Play with clock skew (useful skews).
 7
2. Hold time:
Explain about SETUP and HOLD timing?

 Hold time is the interval after the clock where the

data must be held stable.

 Arrival time > Required time

 Slack hold = Arival time – Required time

• Slack hold < 0 : Hold Violation

• Slack hold > 0 : No hold Violation

 Slack Hold = LFF1 + data – LFF2 – Lib - CU ≥ 0

7 Explain about SETUP and HOLD timing?

 To avoid hold time violations:

• Add delays (using buffers).
• Add lockup-latches (in cases where the hold time requirement is very huge, basically to
avoid data slip).
8
1. Background:
What is OCV? How it affects to timing results?

 The final output which goes to fabrication laboratory from the

ASIC designer is a gds file.

 IC is a fabricated on the silicon wafer as per the gds data.

 Whole wafer is divided into small die and each die contains an
individual IC. Later we cut and separate each die and do IC
Packaging.

 So we have same gds for each ICs but fabricated at different die
having different location on a wafer and different lots of wafers.

 All these variations come from fabrication process.

8 What is OCV? How it affects to timing results?

2. Source of Variations:
8 What is OCV? How it affects to timing results?

2. Source of Variations:

a. Variation in Process:

 Drain current of an NMOS transistor in the linear region:

 Parameters which are dependent on fabrication process:

• Gate Oxide Thickness (tox)

• With of transistor (W)

• Length of the transistor (L)

• Threshold voltage of Transistor (Vt)

8 What is OCV? How it affects to timing results?

 If any of the factors mentioned above varies during the fabrication process, It will affect the drain
current. The delay of a cell is dependent on the drain current so due to process variation, the
delay of a standard cell is going to vary.

 Process variation generally includes:

• Photolithography
• Optical Proximity Correction (OPC)
• Random Dopant Fluctuation (RDF)
• Line Edge Roughness (LER)
• Etching 
• Chemical Mechanical Policing (CMP)
• Oxide Thickness Variation (OTV)
8 What is OCV? How it affects to timing results?

2. Source of Variations:

b. Variation in Voltage:

 Standard cells get power from the power pad though power stripe and rails

 It is fairly possible that the effective interconnect length (rails + stripe) for two standard
cells placed in different locations could be different.

 There will be a variation of available VDD for the standard cells depending on the design.
Delay of a cell is dependent on the available VDD, If VDD is less delay will be more.
8 What is OCV? How it affects to timing results?

2. Source of Variations:

b. Variation in Temperature:

 Transistor characteristic is very strongly dependent on the temperature.

 One factor in ambient temperature on which chip is being operated. But transistor’s characteristics
mainly depends on Junction temperature.

 Junction temperature is sum of ambient temperature and temperature raised due to power
dissipation of transistors.

 Based on placement density and power requirements, there are formation of local hotspot on a
particular area of core.
 9 Research and explain about "useful skew" technique.

 Clock skew (sometimes called timing skew) is a

phenomenon in synchronous digital circuit systems (such
as computer systems) in which the same sourced clock
signal arrives at different components at different times.
The instantaneous difference between the readings of any
two clocks is called their skew.
 What is “Useful Skew” ?
• Most timing violations are fixed by data path optimization.
• With useful skew, you fix timing violations by adjusting
clock arrival times at registers or latches.
 9 Research and explain about "useful skew" technique.

       T ≥ reg  + path (max) + J + S – Skew (setup time)

      Skew ≤ reg + path (min) - J – H (hold time)

• T is the clock period,
• reg is the source register's clock to Q delay,
• path (max) is the path with the longest delay from
source to destination,
• J is an upper bound on jitter,
• S is the setup time of the destination register
• path (min) is the path with the shortest delay
from source to destination,
• H is the hold time of the destination register,
DATA / LIBRARY
10 What are the input/output data of Physical Design?
Explain each kind of data.

Data Input Requirement for Physical Design Tools

File type or format File content
Technology life: It describes the units, drawing patterns, layers, design
+ .tf : Techfile -> In Synopsys (ICC- ICC2) rules, vias, and parasitic resistance and capacitance of
+ .lef: Library Exchange Format -> In Cadence ( EDI – manufacturing process.
Innovus)
Reference libraries: Contain cell timing, functionality, netlist and design rule
+ .lib: Synthesis library files constraints.
+ .db: Data base
GDSII files : Contain the physical layout information; to create
+ .gds (Graphical Data stream) reference libraries.
+.oas (oasis – another format of gds)
Netlist file : .v (Verilog) Contain connectivity Information.
Constraints file : .sdc (Synopsys Design constraint) Contain timing constraint and clock definitions.
DEF files: .def or floorplanelife Netlist and floorplan (cell placement) Information.
10 What are the input/output data of Physical Design?
Explain each kind of data.

Data Output for Physical Design Tools

File type or format File content
Design : .sdf (Synopsys Delay Format) Post-floor plan timing.
Parasitic : .spef (Synopsys Parasitic Extract Format) Parasitic Information.
Updated Verilog : .v(flattened) Optimized netlist
Updated physical layout : .gds./.oas Physical layout information.
Updated design: .def Netlist and floorplan (cell placement) Information.
Updated physical layout : .lef Physical layout, timing and technology Information of
reference libraries.
FRAME/ ABSTRACT Physical Library.
10 TF (Technology File)
 Contain the number of metal layers, vias, their name and conventions.
 Design rules for metal layers (the width of metal layer and spacing between two metal layers).
 Metal layers resistance and capacitance as well as routing grid.
 Unit, precision, color, pattern of metal layer and via.
 Maximum current density is also present in tech file.
 Contain ERC rules, Extraction rules, LVS rules.
 Physical and electrical characteristics of each layer and via.
 Contain n-well, p-well, metal pitch.
 Technology file should be compatible with both physical & timing libraries.
10 Example
10 LIB (Liberty Timing File)
 An ASCII format (with text).
 Provided by semiconductor vendor (TSMC, SAMSUNG, FUJITSU…)
10 LIB (Liberty Timing File)
 Contain timing information of standard cells, soft macros, hard macros.
 Contain functional information of standard cells and soft macros.
 Timing information (cell delay setup, hold, recovery, removal are present).
 Design rules (max tran, max cap, max fanout, min cap are present).
 Contain power information.
 PVT corners (Process, Voltage, Temperature) are also present. Every PVT has a .lib file because
the timing of cells is different.
 Cell delay is a function of input transition and output load, which is calculated based on lookup
tables.
® Design company usually custom these lib information to adapt with product requirement.
10 Example
10 DB

 *.db – Technology Library – a compiled version of *.lib in Synopsys database format.

 Binary format.
 Contain same information as the .lib files but encrypted.
 Using for Physical Design from initial phase.
 EDA tool using *.db will process the job faster than *.lib.
 Trace information easily by *.lib format.
10 GDS/GDSII (Graphic Database System Informa
Intercharge)

 It is a binary file format that represents layout data in a hierarchical format.

 Data such as labels, shapes, layer information and other 2D, 3D layout geometric data.
 This file is then provided to the fabrication plant that uses this file to etch the chip based on the
parameters provided in the file.
 GDS stream out from PNR tools must have GDS layer map file.
 GDSII files are usually the final output product of the IC design cycle and are given to silicon
foundries for IC fabrication
 GDSII files can be read as normal files or gzip compressed files without an external
decompresser.
10 GDS/GDSII (Graphic Database System Informa
Intercharge)

 Oasis is new format of GDS so we can use both of them or convert them.
 Oasis is a smaller file size over GDSII format.
 The smaller file sizes may result in faster loading.
 However, due to its internal structure, increased processor capacity is needed to parse
these files.
 It may nullify performance gains conferred because of smaller file size.
 Oasis file format is not as common as the GDSII file format.
10 CDL (Circuit Description Language)

 Circuit description language (CDL) is a kind of netlist, a description of an electronic circuit. It

is usually automatically generated from a circuit schematic.
 SPICE is another format (.spi or.sp). Simulation Program with Integrated Circuit Emphasis.
 It is used for electronic circuit simulation and layout versus schematic (LVS) checks.
10 DEF (Design Exchange Format)

 Represent the physical layout of an IC in an ASCII format.

 Including the placement and routing information.
 Noted: EDA tool will create new object if it does not exist.
 Logical design data IMPORTED to PNR tools.
 Physical design data EXPORTED from PNR tools and can be IMPORTED to PNR tools.
 Usually, DEF using in Floorplan step.
 Some cases, we can use FP file (dump file) replace DEF.
10 DEF (Design Exchange Format)

Logical design data Physical design data

 Internal connectivity (represented by netlist)  Placement locations and orientations
 Grouping information  Routing geometry data
 Physical constraint  Logical design change
10

LEF
Contain physical information of standard cells, macros, pads.
 Contain the name of the pin, pin location, pin layers, direction of pin (in, out, inout), uses of pin
(Signal, Power, Ground) site row, height and width of the pin and cell.
 Contain the height of standard cell placement rows.
 Macros information (cell name, size, dimensions, layout, blockages and capacitance) are defined.
 Design rules, via definitions, metal layers and metal capacitances are defined.
 For every technology, the via and layer definition are different, so in physical library defined the
type of layer (routing master slice / overlap), width / pitch and spacing, direction, resistance,
capacitance, and antenna factor are defined.
 Contain preferred routing Directions, minimum width of the resolution.
10 LEF
LEF has 2 types of view:

 CELL view : it is a full layout of the block and used at the time of tape out.

 FRAM view : this is an abstract view that has only the pins, metals, via and blockages that

are used in Placement & Route stages. This makes sure that the interconnection between

the pins can be routed automatically and the routing tool will not route over existing

metal/via areas otherwise any shorts will come into the picture.
10 NETLIST
 Textual description of circuits components (logic gates, combinational circuits, sequential circuits),
so netlist is a collection of gates.
 It contains the logical connectivity of all the cells.
 It can also be a collection of resistors, capacitors or transistors.
 PnR designer using Verilog netlist at input of initial phase.
10 SDC (Synopsys Design Constraints)
 These are timing constraints and clock exceptions in SDC.
 Timing Constraints:
 Timing Exceptions:
• Create generated clock
• Virtual clock • Multicycle Path
• Input / output delay
• False Path
• Max / min delay
• Max transition • Half Cycle Path
• Max capacitance
• Disable timing arcs
• Max fanout
• Clock latency • Case analysis
• Clock uncertainty etc.
THANKS!