CT 222: HARDWARE DESCRIPTION
LANGUAGES AND PROGRAMMABLE
LOGIC
Instructor: Mr. Mwalongo M, R
(Assistant Lecturer)
Office No: AB 15 (Admin Block)
E-mail: [email protected]
DIGITAL SYSTEM DESIGN FLOW AND
HARDWARE DESCRIPTION LANGUAGES
(HDLS)
INTRODUCTION
Traditionally, digital system design was a manual process of
designing and capturing circuits using schematic entry tools.
This process has many disadvantages and is rapidly being
replaced by new methods.
System designers are always competing to build cost-
effective products as fast as possible in highly competitive
environment.
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INTRODUCTION
In order to achieve this, top down design methodologies
including Hardware Description Languages (HDLs) and
synthesis and simulation are in use.
A product of this instance is any electronic equipment
containing Application-Specific Integrated Circuits (ASICs),
or Field-Programmable Gate-Arrays (FPGAs)
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INTRODUCTION
Advantages of top design methodology;
Increased productivity yields shorter development cycles with more
product features and reduced time to market.
Reduced non-recurring engineering costs
Design reuse is enabled
Increased flexibility to design changes
Faster exploration of alternative architectures
Faster exploration of alternative technology libraries
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Better and easier design auditing and verification
ASIC AND FPGA DEVICES
ASIC
It is a device that is partially manufactured by an ASIC and
vendor generic form. Its manufacturing process is the most
complex, time consuming, and expensive part of the total
manufacturing process.
There are two types/categories of ASIC devices;
Gate Arrays and;
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Standard Cells
ASIC AND FPGA DEVICES
Gate Arrays are logic gates that are pre-laid in matrix
form on a chip.
Types of gate arrays
Channeled
Non-channeled/channel-less
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ASIC AND FPGA DEVICES
Channeled gate array is manufactured with single or
double rows of basic cells across the silicon.
The channels between the rows of cells are used for
interconnecting the basic cells during the final
customization process.
Channel-less gate array is manufactured with a “sea” of
basic cells across the silicon and there are no dedicated
channels for interconnections. 8
ASIC AND FPGA DEVICES
Standard Cell
In this category devices do not have the concept of a cell
and no components are prefabricated on the silicon chip.
The manufacturer creates custom masks for every stage of
device’s process and means silicon is utilized much more
efficiently than gate arrays.
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ASIC AND FPGA DEVICES
FPGAs
They are integrated circuits designed to be configured by a
customer or a designer after manufacturing – hence the term
"field-programmable".
The FPGA configuration is generally specified using
a hardware description language (HDL), similar to that used
for an application-specific integrated circuit (ASIC).
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ASIC AND FPGA DEVICES
FPGAs
Each FPGA vendor manufactures devices to proprietary
architecture.
Architecture includes an number of programmable logic blocks
that are connected to programmable switching matrices.
To configure a device for a particular functional operation
these switching matrices are programmed to route signals
between the individual logic blocks.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
HDL is a language that describes the hardware of digital
systems in a textual form.
It resembles a programming language, but is specifically
oriented to describing hardware structures and behaviors.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
The main difference with the traditional programming
languages is HDL’s representation of extensive parallel
operations whereas traditional ones represent mostly serial
operations.
The most common use of a HDL is to provide an
alternative to schematics.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
HDL can be used to represent logic diagrams, Boolean
expressions, and other more complex digital circuits.
Thus, in top down design, a very high-level description of
a entire system can be precisely specified using an HDL.
This high-level description can then be refined and
partitioned into lower-level descriptions as a part of the
design process.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
There are two standard HDL’s that are supported by IEEE.
VHDL (Very-High-Speed Integrated Circuits Hardware
Description Language) - Sometimes referred to as
VHSIC HDL, this was developed from an initiative by
US. Dept. of Defense.
Verilog HDL – developed by Cadence Data systems and
later transferred to a consortium called Open Verilog
International (OVI). 15
HDL BASED DIGITAL DESIGN
Why HDLs?
Support larger system designs.
By describing the design in a high-level (=easy to
understand) language, we can simulate our design
before we manufacture it. This allows us to catch
design errors.
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HDL TOOL SUITES
Text editor
Allows you to write, edit and save an HDL program.
Compiler
Finds syntax errors.
Creates an intermediate file that describes the
interconnections and logic operations.
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HDL TOOL SUITES
Synthesizer
Targets the design to a specific hardware technology such
as PLD, FPGA or ASIC.
Refers to one or more libraries having gates, flipflops,
registers, adders, counters etc.
By analyzing the intermediate design description,
synthesizer “infer” the opportunity to map portions of the
design into these larger-scale library components. 18
HDL TOOL SUITES
Simulator
Inputs: HDL program and test bench/ waveform editor.
Test bench is the timed sequence of inputs for the
hardware described by HDL.
Waveform editor used to graphically represent the inputs.
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HDL TOOL SUITES
Simulator
Simulator runs the specified input sequence on the
described hardware and determines the values of
hardware’s internal signals and its outputs over a
specified period of time.
Outputs are viewed graphically through waveform editor
and also a text file that lists signal values, errors and
warnings.
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HDL TOOL SUITES
Template generator
Creates text file with the outline of commonly used program
structure so that the designer can “fill in the blanks” to create
source code for a particular purpose.
Schematic viewer
Creates schematic diagram corresponding to an HDL
program, based on output of compiler.
May differ from final synthesized result.
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HDL TOOL SUITES
Translator
Targets the compiler’s intermediate-language output to a real
device such as PLD, FPGA or ASIC
There is also an associated fitter and chip viewer.
Fitter fits the translated realization into available resources
on the real device.
Chip viewer lets the designer see how the design has been
laid out on the chip. 22
HDL TOOL SUITES
Timing analyzer
Calculates delays through some or all of the signal paths in
the final chip and produces a report showing the worst case
paths and their delays.
Back annotator
Inserts delay clauses or statements in the original HDL
source program, corresponding to delays calculated by the
timing analyzer. 23
HDL –BASED DESIGN FLOW
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FRONT-END STEPS
Block diagram: define modules and their interfaces
Coding: writing of HDL code for modules, their
interfaces and their internal details
Compilation: the HDL compiler analyzes the code for
syntax errors and compatibility with other modules on
which it relies
Simulation: define and apply inputs to the design and
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observe its outputs.
FRONT-END STEPS
Verification:
Functional verification: study the circuit’s logical
operation
Timing verification: study circuit’s operation
including estimated delays ,and verify setup, hold
and other timing requirements
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BACK-END STEPS
Synthesis: converts the HDL description into a set of
primitives or components that can be assembled in the
target technology.
E.g.: with PLDs and CPLDs, the synthesis tool may
generate two-level SOP equations.
With ASICs, it may generate a list of gates and a netlist
that specifies how they should be connected
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BACK-END STEPS
Fitting: a fitter maps the synthesized primitives or
components onto available device resources.
For PLD or CPLD, this means assigning equations to
available AND-OR elements.
For FPGA or ASIC, it means selecting macro-cells or
laying down individual gates in a pattern and finding
ways to connect them within the physical constraints of
the FPGA or ASIC die--- place-and-route process 28
BACK-END STEPS
Timing verification: actual circuit delays due to wire
lengths, electrical loading and other factors can be
calculated with reasonable precision
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THANK YOU!!!!!!!!!!
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