Introduction to FPGA
Presented By
Muhammad Naseem
Asstt. Prof., CED, SSUET
Email:[email protected]
http://www.ssuet.edu.pk/~mnaseem
World of Integrated Circuits
Integrated Circuits
Full-Custom Semi-Custom User
ASICs ASICs Programmable
PLD FPGA
PAL PLA PML LUT MUX Gates
(Look-Up Table)
Two implementation approaches
ASIC FPGA
Designs must be sent for Bought off the shelf
expensive and time and reconfigured by
consuming fabrication in designers themselves
semiconductor foundry
Designed all the way
from behavioral
No physical layout
description to physical design; design ends
layout with a bitstream used
to configure a device
What is an FPGA?
Configurable
Logic
Blocks
I/O
Block RAMs
Block RAMs
Blocks
Block
RAMs
Which Way to Go?
ASICs FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Reconfigurability
Other FPGA Advantages
Manufacturing cycle for ASIC is very costly,
lengthy and engages lots of manpower
Mistakes not detected at design time have large
impact on development time and cost
FPGAs are perfect for rapid prototyping of digital
circuits
Easy upgrades like in case of software
Unique applications
reconfigurable computing
Major FPGA Vendors
SRAM-based FPGAs
Xilinx, Inc. Share over 60% of
Altera Corp. the market
Atmel
Lattice Semiconductor
Flash & antifuse FPGAs
Actel Corp.
Quick Logic Corp.
Xilinx
Primaryproducts: FPGAs and the associated CAD
software
Programmable
Logic Devices ISE (Integrated Software Environment)
Alliance and Foundation
Series Design Software
Xilinx FPGA Families
Old families
XC3000, XC4000, XC5200
Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern
designs.
High-performance families
Virtex (0.22µm)
Virtex-E, Virtex-EM
Virtex-II, Virtex-II PRO
Virtex-4 (0.09µm)
Virtex-5, Virtex-6, Virtex-7
Low Cost Family
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3
FPGA Nomenclature
Spartan-3 Block RAM Amounts
Block RAM Port Aspect Ratios
Block RAM Port Aspect Ratios
1 2
0 4
0
0
8k x 2 4k x 4
4,095
16k x 1 8,191 8+1
0
2k x (8+1)
204
7
16+2
0
102
1024 x (16+2)
16,383 3
Dual Port Block RAM
Spartan-3 FPGA
Device Part Marking
Configurable
Block
Block
Logic
I/O
Multipliers 18 x 18
Virtex-II 1.5V Architecture
Block RAMs
Multipliers 18 x 18
Block RAMs
Multipliers 18 x 18
Block RAMs
Multipliers 18 x 18
Block RAMs
Virtex-II 1.5V
Device CLB Array Slices Maximum BlockRAM Multiplier Distributed
I/O (18kb) Blocks RAM bits
XC2V40 8x8 256 88 4 4 8,192
XC2V80 16x8 512 120 8 8 16,384
XC2V250 24x16 1,536 200 24 24 49,152
XC2V500 32x24 3,072 264 32 32 98,304
XC2V1000 40x32 5,120 432 40 40 163,840
XC2V1500 48x40 7,680 528 48 48 245,760
XC2V2000 56x48 10,752 624 56 56 344,064
XC2V3000 64x56 14,336 720 96 96 458,752
XC2V4000 80x72 23,040 912 120 120 737,280
XC2V6000 96x88 33,792 1,104 144 144 1,081,344
XC2V8000 112x104 46,592 1,108 168 168 1,490,944
Virtex-II Block SelectRAM
Virtex-II BRAM is 18 kbits
Additional “parity” bits available
in selected configurations
Width Depth Address Data Parity
1 16,386 [13:0] [0] N/A
2 8,192 [12:0] [1:0] N/A
4 4,096 [11:0] [3:0] N/A
9 2,048 [10:0] [7:0] [0]
18 1,024 [9:0] [15:0] [1:0]
36 512 [8:0] [31:0] [3:0]
Programmable ASIC Logic
Cells
All Programmable ASICs or FPGAs contain a basic
logic cell replicated in a rectangular array across the
chip
Basic internal structure
PLB
Programmable Logic Blocks
PI
Programmable Interconnect
Types of basic logic cells
multiplexer based
look-up table based
programmable array logic
Actel ACT
The basic logic cells in the Actel ACT family
of FPGAs are called Logic Modules
The Actel ACT 1 Family uses just one type of
Logic Module
Actel ACT 2 and ACT 3 FPGA families use
two different types of Logic Modules
ACT 1 Logic Module
Architecture
The functional behavior of ACT 1 logic module is described by the
following diagram
Multiplexers
Since the Structure dictates us to implement
logic functions as 2:1 Multiplexers therefore
we take a brief look about Multiplexers
Topics
Synthesis of Logic Functions using Multiplexers
Multiplexer Synthesis using Shannon’s Expansion
A 2:1 Multiplexer
A 4:1 Multiplexer
Using 2-to-1 multiplexers to
build a 4-to-1 multiplexer
Synthesis of a Logic Function
using Multiplexers
3-input Majority Function
Multiplexer Synthesis
using Shannon’s Expansion
Multiplexers may be used for synthesis
(connection) of more complex circuit inputs.
So overall circuits is realized using both logic
gates and multiplexers
Shannon’s Expansion
Theorem
Any Boolean function f(w1,w2,…,wn) can be written in the form
This expression can be done in terms of any of the n variables
Example
Example:
Expand F with respect to A
F = A' · B + A · B · C' + A' · B' · C
= A' · (B + B' · C) + A · (B · C')
Cofactor of F wrt A = B · C‘, cofactor F wrt A’ = B + B' · C
F with respect to B
F =B' · (A' · C) + B · (A' + A · C')
We can continue to expand a function until we reach the
canonical form; a unique representation that uses only
minterms
minterm is a product term that contains all the variables of F
Another Example
F = (A · B) + (B' · C) + D
= (A · B) + (B' · C) + [D ·(B + B’)]
= B’·(C+D) + B·(A+D) = B’·F1 + B F2
Suppose we expand F2 = F B wrt A, and F1 = F B' wrt C
F1 = C + D = C + D·(C + C’) = C + C’·D = C’ ·D + C·1
F2 = A + D = A + D·(A + A’) = A + A’·D = A’ D+ A·1
Implementation
A0 = D, A1 = 1, SA = C (F1)
B0 = D, B1 = 1, SB = A (F2)
S0 = 0, S1 = B
Exercise
Implement a 3-input NAND Gate using ACT1 Logic Module?
FAQ?
