The ARM

Instruction Set

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
TM
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 Agenda

Introduction to ARM Ltd

Programmers Model
 Instruction Sets
System Design
Development Tools

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 All states
have equal
time period –
ARM feature -
advantage

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 ARM MEMORY

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MEMORY
ORGANISATION

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 ARM
INSTRUCTION SET

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 Condition Codes

 The possible condition codes are listed below:

 Note AL is the default and does not need to be specified

Suffix Description Flags tested

EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Minus N=1
PL Positive or Zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 & Z=0
LS Unsigned lower or same C=0 or Z=1
GE Greater or equal N=V
LT Less than N!=V
GT Greater than Z=0 & N=V
LE Less than or equal Z=1 or N=!V
AL Always

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 Branch instructions
 Branch : B{<cond>} label
 Branch with Link : BL{<cond>} subroutine_label

31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch

1 = Branch with link
Condition field

 The processor core shifts the offset field left by 2 positions, sign-extends
it and adds it to the PC
 ± 32 Mbyte range
 How to perform longer branches?

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 Conditional Execution and Flags

 ARM instructions can be made to execute conditionally by postfixing

them with the appropriate condition code field.
 This improves code density and performance by reducing the number of
forward branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip

 By default, data processing instructions do not affect the condition code

flags but the flags can be optionally set by using “S”. CMP does not
need “S”.
loop
… decrement r1 and set flags
SUBS r1,r1,#1
BNE loop if Z flag clear then branch

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 Examples of conditional
execution
 Use a sequence of several conditional instructions
if (a==0) func(1);
CMP r0,#0
MOVEQ r0,#1
BLEQ func

 Set the flags, then use various condition codes

if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1

 Use conditional compare instructions

if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0

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 Data processing Instructions
 Consist of :
 Arithmetic: ADD ADC SUB SBC RSB
RSC
 Logical: AND ORR EOR BIC
 Comparisons: CMP CMN TST TEQ
 Data movement: MOV MVN

 These instructions only work on registers, NOT memory.

 Syntax:

<Operation>{<cond>}{S} Rd, Rn, Operand2

 Comparisons set flags only - they do not specify Rd

 Data movement does not specify Rn

 Second operand is sent to the ALU via barrel shifter.

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 The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift

CF Destination 0 Destination CF

Multiplication by a power of 2 Division by a power of 2,

preserving the sign bit

LSR : Logical Shift Right ROR: Rotate Right

...0 Destination CF Destination CF

Division by a power of 2 Bit rotate with wrap around

from LSB to MSB

RRX: Rotate Right Extended

Destination CF

Single bit rotate with wrap around

from CF to MSB

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 Using the Barrel Shifter:
The Second Operand
Register, optionally with shift operation
Operand Operand  Shift value can be either be:
1 2  5 bit unsigned integer
 Specified in bottom byte of another
register.
 Used for multiplication by constant
Barrel
Shifter

Immediate value
 8 bit number, with a range of 0-255.
 Rotated right through even number of
positions
ALU  Allows increased range of 32-bit
constants to be loaded directly into
registers

Result

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 Immediate constants (1)

 No ARM instruction can contain a 32 bit immediate constant

 All ARM instructions are fixed as 32 bits long
 The data processing instruction format has 12 bits available for operand2

11 8 7 0
rot immed_8
Quick Quiz:
x2 0xe3a004ff
Shifter
ROR MOV r0, #???

 4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2
 Rule to remember is “8-bits shifted by an even number of bit positions”.

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 Immediate constants (2)
 Examples:
31 0
ror #0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 range 0-0x000000ff step 0x00000001

ror #8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 range 0-0xff000000 step 0x01000000

ror #30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 range 0-0x000003fc step 0x00000004

 The assembler converts immediate values to the rotate form:

 MOV r0,#4096 ; uses 0x40 ror 26
 ADD r1,r2,#0xFF0000 ; uses 0xFF ror 16

 The bitwise complements can also be formed using MVN:

 MOV r0, #0xFFFFFFFF ; assembles to MVN r0,#0

 Values that cannot be generated in this way will cause an error.

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 Loading 32 bit constants

 To allow larger constants to be loaded, the assembler offers a pseudo-

instruction:
 LDR rd, =const

 This will either:

 Produce a MOV or MVN instruction to generate the value (if possible).

or
 Generate a LDR instruction with a PC-relative address to read the constant
from a literal pool (Constant data area embedded in the code).
 For example
 LDR r0,=0xFF => MOV r0,#0xFF
 LDR r0,=0x55555555 => LDR r0,[PC,#Imm12]
…
…
DCD 0x55555555
 This is the recommended way of loading constants into a register

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 Multiply
 Syntax:
 MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs
 MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn
 [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs
 [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo

 Cycle time
 Basic MUL instruction
 2-5 cycles on ARM7TDMI
 1-3 cycles on StrongARM/XScale
 2 cycles on ARM9E/ARM102xE
 +1 cycle for ARM9TDMI (over ARM7TDMI)
 +1 cycle for accumulate (not on 9E though result delay is one cycle longer)
 +1 cycle for “long”

 Above are “general rules” - refer to the TRM for the core you are using
for the exact details

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 Single register data transfer

LDR STR Word

LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load

 Memory system must support all access sizes

 Syntax:
 LDR{<cond>}{<size>} Rd, <address>
 STR{<cond>}{<size>} Rd, <address>

e.g. LDREQB

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 Address accessed

 Address accessed by LDR/STR is specified by a base register plus an

offset
 For word and unsigned byte accesses, offset can be
 An unsigned 12-bit immediate value (ie 0 - 4095 bytes).
LDR r0,[r1,#8]
 A register, optionally shifted by an immediate value
LDR r0,[r1,r2]
LDR r0,[r1,r2,LSL#2]
 This can be either added or subtracted from the base register:
LDR r0,[r1,#-8]
LDR r0,[r1,-r2]
LDR r0,[r1,-r2,LSL#2]
 For halfword and signed halfword / byte, offset can be:
 An unsigned 8 bit immediate value (ie 0-255 bytes).
 A register (unshifted).
 Choice of pre-indexed or post-indexed addressing

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 Pre or Post Indexed Addressing?
 Pre-indexed: STR r0,[r1,#12]
Offset r0
Source
12 0x20c 0x5 0x5 Register
for STR
r1
Base
Register 0x200 0x200

Auto-update form: STR r0,[r1,#12]!

 Post-indexed: STR r0,[r1],#12

Updated r1 Offset
Base 0x20c 12 0x20c
Register r0
Source
Original r1 0x5 Register
Base 0x5 for STR
0x200
Register 0x200

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 LDM / STM operation
 Syntax:
<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>
 4 addressing modes:
LDMIA / STMIA increment after
LDMIB / STMIB increment before
LDMDA / STMDA decrement after
LDMDB / STMDB decrement before
IA IB DA DB
LDMxx r10, {r0,r1,r4} r4
STMxx r10, {r0,r1,r4} r4 r1
r1 r0 Increasing
Base Register (Rb) r10 r0 r4 Address
r1 r4
r0 r1
r0

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 Software Interrupt (SWI)
31 28 27 24 23 0

Cond 1 1 1 1 SWI number (ignored by processor)

Condition Field

 Causes an exception trap to the SWI hardware vector

 The SWI handler can examine the SWI number to decide what operation
has been requested.
 By using the SWI mechanism, an operating system can implement a set
of privileged operations which applications running in user mode can
request.
 Syntax:
 SWI{<cond>} <SWI number>

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 PSR Transfer Instructions
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q J U n d e f i n e d I F T mode
f s x c

 MRS and MSR allow contents of CPSR / SPSR to be transferred to / from

a general purpose register.
 Syntax:
 MRS{<cond>} Rd,<psr> ; Rd = <psr>
 MSR{<cond>} <psr[_fields]>,Rm ; <psr[_fields]> = Rm

where
 <psr> = CPSR or SPSR
 [_fields] = any combination of ‘fsxc’
 Also an immediate form
 MSR{<cond>} <psr_fields>,#Immediate
 In User Mode, all bits can be read but only the condition flags (_f) can be
written.

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 ARM Branches and Subroutines
 B <label>
 PC relative. ±32 Mbyte range.
 BL <subroutine>
 Stores return address in LR
 Returning implemented by restoring the PC from LR
 For non-leaf functions, LR will have to be stacked
func1 func2
STMFD sp!, :
: {regs,lr}
:
: :
:
BL func1 BL func2
:
: :
:
: LDMFD sp!,
{regs,pc} MOV pc, lr

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 Thumb
 Thumb is a 16-bit instruction set
 Optimised for code density from C code (~65% of ARM code size)
 Improved performance from narrow memory
 Subset of the functionality of the ARM instruction set
 Core has additional execution state - Thumb
 Switch between ARM and Thumb using BX instruction
31 0
ADDS r2,r2,#1
32-bit ARM Instruction
For most instructions generated by compiler:
 Conditional execution is not used
 Source and destination registers identical
 Only Low registers used
 Constants are of limited size
15
ADD r2,#1
0  Inline barrel shifter not used
16-bit Thumb Instruction

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 Agenda

Introduction
Programmers Model
Instruction Sets
 System Design
Development Tools

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 Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM

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 AMBA
Arbiter Reset

ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External

Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller

AHB or ASB APB

System Bus Peripheral Bus

 AMBA  ACT
 Advanced Microcontroller Bus  AMBA Compliance Testbench
Architecture
 ADK  PrimeCell
 Complete AMBA Design Kit  ARM’s AMBA compliant peripherals

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 Agenda

Introduction
Programmers Model
Instruction Sets
System Design
 Development Tools

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 The RealView Product Families

Compilation Tools Debug Tools Platforms

ARM Developer Suite (ADS) – AXD (part of ADS) ARMulator (part of ADS)
Compilers (C/C++ ARM & Thumb), Trace Debug Tools Integrator™ Family
Linker & Utilities
Multi-ICE
Multi-Trace

RealView Compilation Tools (RVCT) RealView Debugger (RVD) RealView ARMulator ISS
(RVISS)
RealView ICE (RVI)
RealView Trace (RVT)
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 ARM Debug Architecture
Ethernet

Debugger (+ optional
trace tools)

JTAG port Trace Port

 EmbeddedICE Logic
 Provides breakpoints and processor/system
access
TAP
 JTAG interface (ICE) controller
 Converts debugger commands to JTAG ETM
signals
EmbeddedICE
 Embedded trace Macrocell (ETM) Logic
 Compresses real-time instruction and data
access trace
 Contains ICE features (trigger & filter logic)
ARM
 Trace port analyzer (TPA) core
 Captures trace in a deep buffer

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