COUNTER CHAPTER

4
LEARNING OUTCOME

• Draw circuit and timing diagram of asynchronous

counters.
a) Asynchronous up counter
b) Asynchronous counters as a frequency divider
c) Asynchronous down counter
d) Asynchronous up/down counter
e) Asynchronous counter mode number < 2n
f) Decade (mode 10) counters
 INTRODUCTION

• There are two(2) types of counter which are

synchronous counter and asynchronous counter.
• The differences between this two counter are:
a) AC has high propagation delay time
compared with SC. This is because AC has a FF
that gets triggered FF hour from the previous
release. SC has a FF that gets triggered clock
simultaneously.
 INTRODUCTION

“1” “1”

J J
QA QB

clk clk

K K QB
QA 5V

Figure 5.3 (a) : 2-Bit Asynchronous Counter

J J QB
QA

CLK CLK

K K
QA QB

Figure 5.15(a) : Mod 4 Synchronous Up Counter

 INTRODUCTION

b) AC counting consecutively either

upward or downward, while the SC can
count random.
c) AC has a simple circuit compared SC
with a complex circuit
ASYNCHRONOUS COUNTER

 The equivalent name is Ripple Counter.

 The clock input is applied only to the first
flip- flop, also called the input flip-flop, in
the cascaded arrangement.
 For instance, the output of the first flip-
flop acts as the clock input to the second
flip-flop, the output of the second flip-flop

feeds the clock input of the third flip-flop

ASYNCHRONOUS COUNTER

 The equivalent name is Ripple Counter.

 The clock input is applied only to the first
flip- flop, also called the input flip-flop, in
the cascaded arrangement.
 For instance, the output of the first flip-
flop acts as the clock input to the second
flip-flop, the output of the second flip-flop

feeds the clock input of the third flip-flop

ASYNCHRONOUS COUNTER

Asynchronous counter are divided into three

type .

• Asynchronous up counters – counting up

(minimum to maximum number)
• Asynchronous down counters – counting
down (maximum to minimum number)
• Asynchronous up/down counters – capable
of counting up or counting down.
ASYNCHRONOUS COUNTER
 Asynchronous Up counter can count from
minimum number to maximum number.
 If Mod-8 up counter, the sequence will be 0, 1,
2, 3, 4, 5, 6, 7, 0, 1, 2,
 The other name for Mod-8 counter is 3-bit
counter.
 If 2-bit counter, the sequence will be 0, 1, 2, 3,
0, 1,
 The other name for 2-bit counter is Mod-4
counter.
2- BIT ASYNCHRONOUS COUNTER

“1” “1”

J J
QA QB

clk clk

K
K QB
QA

Figure 5.3 (a) : 2-Bit Asynchronous Counter

2- BIT ASYNCHRONOUS COUNTER

clk 1 2 3 4

QA toggle Qn toggle Qn toggle Qn

QB toggle Qn Qn Qn toggle

Binary 00 01 10 11 00
number

Waveforms for Mod-4 Asynchronous Counter

2- BIT ASYNCHRONOUS COUNTER

Counting sequence Table

Positive edge clock QB QA

0 0 0
1 0 1
2 1 0
3 1 1
4 0 0
2- BIT ASYNCHRONOUS COUNTER

start
Clk 4
00 Clk 1

11 01

Clk 3 10 Clk 2

State Diagram For 2-Bit Counter

METHODS TO DESIGN ASYNCHRONOUS
UP COUNTER
1) Get the number of flip-flop necessity.
Do you remember
Expression for modulus (N) is; how this expression
N = 2n ; where, n = number of flip- flop produced?

So, the number of flip-flop, n = LogN/Log 2 N = 2n  (1)

Log the equation (1)
Example: mod 16 counter (N=16) log N = log 2n, log N =
So the number of flip-flop necessity, n log 2

n = Log 16/Log2 =4 So, n = LogN/Log2

METHODS TO DESIGN ASYNCHRONOUS
UP COUNTER

2) Largest or maximum decimal number want counted.

If mod 16 it would count number 012………15 and
repeat, then largest decimal number was 15. On the whole
its, if N = 2n,  then decimal number maximum counted was
N - 1.

3) State diagram
or sequence table was figure which showed number model
counted namely 01…….. (N-1) and repeat.
METHODS TO DESIGN ASYNCHRONOUS
UP COUNTER

4) Build counter circuit

External clock (clk) connected to first flip-flop. Q's
product each flip-flop are joined at clock input for
flip-flop further. Make sure J's input and K or T at all
flip-flop connected to logic ‘1'.
 EXAMPLE

Build counter circuit for asynchronous mode 8

using JK's flip-flop.
Solution
1) N = modulus = 8, so: FF number = Log 8/Log2=3
2) Largest decimal number counted = N-1 =8-1=7
3) State Diagram
000 001
111 010

011
110
101 100
 EXAMPLE

4) The circuit
‘1’ J QA ‘1’ J QB ‘1’ J Qc

jam CL CL CL
K K K

K K K
 EXAMPLE

5) Timing diagram
clk 1 2 3 4 5 6 7 8

QA

QB

QC
0 1 2 3 4 5 6 7 0

Waveforms for mod 8 counter

EXERCISE
 FREQUENCY DIVIDER CIRCUIT

• When one clock pulse triggered in clock input JK's flip-flop connected
in toggle, frequency output in Q will become half from clock input
frequency.
• If another flip-flop connected like those demonstrated at figure 5-5(i),
clock frequency will be divided into two division on each output flip-
flop. “1”
“1”

• Frequency output can be stated as,

fout= fin/2n , where n = flip-flop number. J
QA
J
QB

CLK
• Division factor = 2n, fin CLK
K K

where n = flip-flop number

Figure 5.5(i) : 2-Bit Asynchronous Counter
as Frequency Divider Circuit
 ASYNCHRONOUS DOWN COUNTER

• This counter would count from maximum number to

minimum number.
“1” “1”

J J
QA QB

CLK CLK

K K
QA QB
ASYNCHRONOUS DOWN COUNTER

clk 1 2 3 4

QA toggle Qn toggle Qn toggle Qn

QB toggle Qn Qn Qn toggle Qn Qn

00 11 10 01 00
ASYNCHRONOUS DOWN COUNTER

Counting Sequence
Positive edge clock QB QA
0 0 0
1 1 1
2 1 0
3 0 1
 RIPPLE COUNTER WITH MODULUS
LESS THAN 2n (N<2n)
• Counter mod N < 2n allow counter ‘skip' some state. This counter
circuit used ‘reset' method. The methods were as follows:-

i. Determine flip-flop number of necessity.

ii. If m = a bigger number from log2 N, then flip-flop number = m.

iii. Connect clock input to the first flip-flop. Q's output of each flip-
flop is connected to clock input of flip- flop further. Make sure J's

input and K or T gives flip-flop altogether in logic ‘1'.

iv. Determine flip-flop output with logic ‘1' in N's number

connected to NAND gate input. NAND gate output attaches to
‘clear' input at all flip-flop.
 EXAMPLE

Build circuit for mod 6 asynchronous counter using JK's flip-flop.

Table shows counting sequence of mod 6

counter
C B A
0 0 0
0 0 1
0 1 0 After counter count 101
0 1 1 it will continue reset to
000 not to 110.
1 0 0
1 0 1
0 0 0
 EXAMPLE

Build circuit for mod 6 asynchronous counter using JK's flip-flop.

QA

QB
‘1’
J QA J QB J QC
QC

Clk CLK CLK clk

K clr K clr K clr

Mod 6 Asynchronous Counter Circuit.

 DECADE COUNTER

Decade counter or mod 10 (having 10 outputs which differ)

and also known as divisor 10, can count from 0(0000) to 9
(1001).
 QUESTION

1- Build circuit for mod 7 asynchronous counter

using JK's flip-flop.
2- Build circuit for mod 9 asynchronous counter
using T's flip-flop.
3- Build circuit for mod 12 asynchronous
counter using JK's flip-flop.
4- Build circuit for mod 13 asynchronous
counter using T's flip-flop.
5- Build circuit for mod 14 asynchronous
counter using JK's flip-flop.
SYNCHRONOUS COUNTER

Advantages
Disadvantag
Each flip- es
flop
Circuit is
received
fairly
simultaneou
complex
s clock pulse
METHODS TO BUILD SYNCHRONOUS
COUNTER
Determine flip-flop number of necessity.

If m = Sebutan maximum n = flip-flop number = log m+1/Log

2

Draw state diagram or counting sequence in binary number.

Fill in excitation table

METHODS TO BUILD SYNCHRONOUS
COUNTER

J
D K
T

GENERAL
EXCITATION TABLE
METHODS TO BUILD SYNCHRONOUS
COUNTER

Wanted Exchange Input State

Qn Qn+1 J K T D
0 0 0 x 0 0
0 1 1 x 1 1
1 0 x 1 1 0
1 1 x 0 0 1
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5
a. Flip – flop number = (Log m +1 ) / (Log 2)
= Log 4+1 / Log 2
= 2.32
= 3FF

b. State Diagram

000 001 010 011 100

EXAMPLE: SYNCHRONOUS COUNTER
MOD 5
c. Excitation Table
Qn Qn+1 INPUT
A B C A B C JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ 0 0 X X C’ X X X 1

C 0 1 X X C X X X X

JA = QBQC KA = 1
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ 0 X X 0 C’ X 0 X X

C 1 X X X C X 1 X X

JB = QC KB = QC
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ 1 1 X 0 C’ X X X X

C X X X X C 1 1 X X

JC = QA’ KC = 1
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5

e. Circuit

JC QC JB QB JA QA

KC QC’ KB QB’ KA QA’

‘1’ ‘1’
EXAMPLE: SYNCHRONOUS COUNTER
MOD 5

f. Timing diagram
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5
a. Flip – flop number = (Log m+1) / (Log 2)
= Log 5+1 / Log 2
= 2.58
= 3FF

b. State Diagram

001 011 101

EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

c. Excitation Table

Qn Qn+1 INPUT
A B C A B C JA KA JB KB JC KC
0 0 1 0 1 1 0 X 1 X X 0
0 1 1 1 0 1 1 X X 1 X 0
1 0 1 0 0 1 X 1 0 X X 0
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ X X X X C’ X X X X

C 0 1 X X C X X X 1

JA = QB KA = 1
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ X X X X C’ X X X X

C 1 X X 0 C X 1 X X

JB = QA’ KB = 1
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

d. Karnaugh Map
A’B’ A’B AB AB’ A’B’ A’B AB AB’

C’ X X X X C’ X X X X

C X X X X C 0 0 X 0

JC = 0 KC = 0
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

d. Circuit

JC QC JB QB JA QA

KC QC’ KB QB’ KA QA’

‘1’ ‘1’
‘0’
EXAMPLE: SYNCHRONOUS COUNTER
COUNT 1,3,5

e. Timing diagram
SYNCHRONOUS UP/DOWN COUNTER

P P
‘1’

J A J B J C
11 21

UP/

K K K

Q Q

Clk

Figure 5.18: Synchronous Up/Down Counter Mod 8

SYNCHRONOUS UP/DOWN COUNTER

Count Up Process

Count Down Process

 CASCADE CONNECTION

• Counter may be connected in cascade (serial) to achieve higher modulus.

• A counter circuit when output on final flip-flop connected to first flip-flop
entry from counter further, then that counter is called connected in cascade.
• If synchronous counter connected in cascade like asynchronous counter circuit,
it will be produced propagation delay.
• To overcome this problem, many integrated circuit for synchronous counter
added with another input known as variable entry ('enable input') and another
product which is known as ‘terminal count' or known also V max, ‘ripple
clock' or ‘carry output'.
• With this input and output terminal, counter output would become maximum.
• Input function ‘count enable' are enabled the counting process ‘terminal count'
is to move integrated circuit counter further when counter achieve maximum
number or produce high yield when counting process produce maximum
number.
CASCADE CONNECTION
CASCADE CONNECTION
 INTEGRATED CIRCUIT OF
ASYNCHRONOUS COUNTER

• The integrated circuit of asynchronous

counter often used is like 7490, 7492 and
7493.
 INTEGRATED CIRCUIT OF
SYNCHRONOUS COUNTER

• The integrated circuit for synchronous counter

was 74LS160, 74LS161, 74LS162, 74LS163,
74LS190, 74LS191, 74LS192 and 74LS193
• 74LS193 is from CMOS type