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Chapter – 2
PIC Micro Controller
PIC = Peripheral Interface
Controller
PIC Micro-Controller
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One of the leading Architecture for low
end applications
PICs are “RISC” (Reduced Instruction
Set Computers)
PIC Micro-Controller
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Few instructions (< 50)
Has only a few addressing modes
Executes 1 instruction in 1 internal
clock cycle (Tcyc)
The PIC Family: Speed
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PICs require a clock to work
• Can use crystals, clock oscillators, or even
Resister Capacitor (RC) circuits
• Some PICs have a built in 4MHz RC clock
• Instruction speed = ¼ clock speed (Tcyc =
4*Tclk)
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Clocking Scheme
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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLK
Q1
Q2
Q3
Q4
PC PC PC+1 PC+2
Instruction Execution
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Clock internally divided by 4 to
generate 4 quadrature clocks.
Instruction cycle consists of 4 Q.
PC is incremented every Q1.
Instruction Execution
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Instruction is fetched from program &
latched into instruction register by Q4
Instruction is decoded & executed in
the following Q1 to Q4.
Instruction Pipelining
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Fetch takes one cycle, decode & execute
takes another cycle.
While execution, next instruction can
be fetched
• No bus conflict due to Harvard architecture.
If instruction changes PC (e.g. Branch)
extra cycle is required to complete
instruction.
ALU
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8 bit
from instruction word
Register
file
Word 8 bit register value
register From direct or
indirect addressing Special
of instruction Function
Registers
(SRRs)
&
ALU General
Purpose
RAM
(GPR)
d=0 d=1
d = destination bit
Status Register
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Status register contains
• Arithmetic status of ALU operations.
• RESET status
• Memory bank select bits
IRP RP1 RP0 TO PD Z DC C
TO: Time Out; PD: Power Down; IRP, RP1, RP0: bank
selects; DC: Digital Carry (BCD); Z: Zero; C: Carry
Memory Organization
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Data Memory
Program Memory
Access to both possible in each cycle
b/c of distinct bus.
The PIC Family: Program Memory
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EPROM (Erasable Programmable Read
Only Memory)
• One Time Programmable (OTP) chips are EPROM
chips, but with no window.
FLASH
• Re-writable
• Much faster to develop
The PIC Family: Program Memory
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Mid-range PIC processors have 13 bit
program counter.
Width of program memory bus is 14
bits.
Program memory space divided into 4
pages of 2k each.
Memory Map
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Stack
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Mid-range PIC 8-level deep 13 bit wide
hardware stack.
PC is pushed onto the stack when CALL
instruction is executed or Interrupt
occurs.
The PIC Family: Data Memory
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PICs use general purpose “file
registers” for RAM (each register is 8
bits for all PICs)
Registers
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GPR - Area banked to provide greater
than 96 bytes of general purpose RAM.
SFR – To control the peripherals & core
function like indirect addressing.
PIC Instruction Set
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Simple instruction set: about 35
instructions
Instruction set grouped into 3
categories
• Byte-Oriented Operation
• Bit-Oriented Operation
• Literal & Control Operation
Cont…
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Instructions: 14 bit (mid-range)
All instructions take one cycle unless
conditional test is true or PC is changed
as a result of an instruction.
Instruction Format
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Byte-Oriented Operation
• 0..6: 7 bit file register address
• 7: d bit; 0 for destination W
• 8..13: opcode
Bit-Oriented Operation
• 0..6: 7 bits file register address
• 7..9: 3 bits bit addresses within the 8-bit file
register
• 10..13: opcode
Instruction Format
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Literal & control operations
• General
0..7: 8 bit literal (immediate) value
8..13: opcode
• CALL & GOTO instructions
0..10: 11 bits literal value (target address)
11..13: opcode
Upper 2 bits of PC loaded from PCLATH<4:3>
Addressing Mode
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Direct Addressing Mode
RP1 RP0 6 0
00 01 10 11
00h
In status register
Data Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Indirect Addressing Mode
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Full 8-bit register file address is first
written into FSR, a special purpose
register.
FSR serves as address pointer to many
address through out entire register file.
Indirect Addressing Mode
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Subsequent direct address of INDF will
actually access the register file using
the contents of FSR as a point to the
location of operand.
Instructions
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Byte-Oriented Operations
• Arithmetic & logical operation
• Data movement
Examples
• addwf f,d
Add contents of W with the register f, if d=0
store result in W else in register f.
• E.g.: addwf 0x20,0
Instructions
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• clrf f
Contents of register f are cleared & Z bit
(STATUS) is set
• E.g.: clrf 0x30
• movwf f
Move data from W register to register f.
• E.g.: movwf 0x04
Instructions
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• decfsz f,d (Conditional)
Decrement register f, place the result in f or w
depending on the value of d; Skip the next
instruction if result is zero.
• E.g.: decfsz 0x20,1
• decf f,d
Decrement f, places result depending on value
of d, effects Z flag
• E.g.: decf 0x30,0
Instructions
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Literal Operations
• Immediate Addressing Mode
Examples
• addlw k
Add literal k to register W.
• E.g.: addlw 0x50
• movlw k
Move literal k into register W.
• E.g.: movlw 0x21
More on data transfer instructions
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Instruction CLRF writes constant 0 in
“f” register, and CLRW writes constant
0 in W register.
SWAPF instruction exchanges places of
the 4-bit nibbles field inside a register.
More on Arithmetic & Logic instruction
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PIC micro-controllers support only
subtraction and addition.
• Flags C, DC, & Z are set depending on a result
of addition or subtraction.
• Since subtraction is performed like addition of
a negative value, C flag is inverse.
More on Arithmetic & Logic instruction
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Logic unit of PIC has capability of
performing operations AND, OR, EX-OR,
Complementing (COMF) and Rotation (RLF
& RRF)
Rotation Instructions
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Rotates the register contents through
flag C
Bits move by one bit to left towards bit
7, or to the right towards bit 0.
Rotation Instructions
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Bit which comes out of a register is written
in flag C, and value of C flag is written in a
bit on the opposite side of the register.
Example
• rrf f,W
Copy f into W, rotate W to right through the carry
flag.
Instructions
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Bit Oriented Operations
• Manipulate bit in control & status registers
Examples
• bsf f,b
Set bit b (where b=0 to 7) in register f.
• E.g.: bsf 0x30,5
• btfsc f,b
Test bit b of register f, skip next instruction if bit
is 0
• E.g.: btfsc 0x03,2
More on bit operation
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Instructions bcf and bsf performs set
or clear one bit anywhere in the
memory
Bit operations consists of the ff micro-
operation
• CPU reads the complete byte
• CPU changes one bit in it
• Then writes the entire byte back
Instructions
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Control Instructions
• Program & processor control
Examples
• goto k(k-11 bit)
Unconditional branch. Literal k is loaded into PC
• E.g.: goto there (use labels)
• call k
Call subroutine at location k
• E.g.: call sum
Instructions
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Examples
• retfie
Return from interrupt service routine & re-enable
interrupt
• sleep
Go to standby mode
• clrwdt
Clear watchdog timer.
Direct program flow
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RETLW k instruction is identical with
RETURN instruction except that before
coming back from a subprogram a
constant defined by instruction
operand k is written in W register.
Example Code
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Decrement a 16 bit counter
Upper byte of the counter COUNTH & lower byte
COUNTL.
movf COUNTL, f ; set Z if lower byte =0
btfsc STATUS, Z ;if so, decrement COUNTL
decf COUNTL, F
decf COUNTH, F ;decrement COUNTH
Example Code
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This program puts out a square wave
on PORTA Pin 0.
clrf PORTA ; Clear PORTA register
clrf TRISA ;Make PORTA all outputs
Loop bsf PORTA, 0 ;Turn on PORTA pin 0
nop ;delay
nop ;delay
bcf PORTA,0 ;Turn off PORTA pin 0
goto Loop ;loop back
Example: Branching
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Set EqualFlag if PORTA = PORTB
bcf EqualFlag,7 ; First clear the flag
movf PORTA,W ;Move PORTA to W
subwf PORTB, W
btfsc STATUS, Z ;Check Z bit
bsf EqualFlag,7 ;ports equal, set flag
The PIC Family: Peripherals
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Different PICs have different on-board
peripherals
Some Common peripherals are:
• Tri-state digital I/O pins
• Analog to digital converters (ADC)
• Serial Communications: UART
• Timer and counter
• others
Interrupts
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An interrupt is any service request that
causes the CPU to stop its current
execution stream & to execute an
instruction stream that services the
interrupt.
When the CPU finishes servicing the
interrupt, it returns to the original
execution stream at the point where it
left out.
Interrupts
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Interrupt driven I/O can be used for
interfacing with on chip peripherals.
Interrupts in PIC
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Source of interrupts are many
• INT pin interrupts from external source
• PORTB change interrupt (RB7:RB4)
• USART interrupts
• A/D conversion interrupt
• LCD interrupts
• Others
Interrupts Management
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Use of register INTCON: Status &
Control
• Bit 7: Global interrupt enable
Enable (if set) all unmasked interrupts or
disables all interrupts
Interrupts Management
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• Bits 6,5,4,3: For enabling peripheral, timer0,
external interrupt, Port B bit change interrupts
respectively.
• Bits 2,1,0: Timer0, INT, port change interrupt
flag respectively
Flag bits get set when interrupt occurs
regardless of the value of enable bit.
Peripheral Interrupts
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Managed using PIE & PIR registers
PIE contain bits for enabling interrupts
from individual peripherals
PIR registers contain flag bits for
individual peripheral interrupts
Bit oriented instructions can be used to
examine and/or manipulate interrupt
control & status registers.
Interrupt Processing
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When interrupt is responded to
• GIE bit is cleared to disable other interrupts
• PC is pushed onto the stack
• PC is loaded with 0004h.
• Save STATUS & W in temporary memory
location.
Return from interrupt instruction
(retfie) exists ISR, sets GIE bit to allow
pending interrupts to execute.
Interrupt Constraints
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Each interrupt source characterized by
• Minimum time interval b/n interrupts from the
same source
• Maximum time it takes the CPU to execute
interrupt source handle.
Servicing of interrupts must not be
delayed beyond the limit imposed by
the timing requirement of the source.
Critical Region
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A critical region is a sequence of
instructions that must be protected
from an intervening interrupt
In PIC this problem is handled by
• Single cycle read-modify-write instruction
xorwf PORTD F
PORTD data read, XORed with W &
written back to PORTD
Disabling interrupts by clearing GIE
PIC Peripherals: Digital I/O
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All PICs have digital I/O pins called
ports.
Ports are used to control & monitor
external devices.
Ports have 2 control registers
• TRISX sets whether each pin is an input or
output
• PORTX sets their output bit levels
Example: Port A
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All pins are I/O with associated
direction bits in TRISA
Initialization code:
clrf STATUS ; bank 0
clrf PORTA ;initializing by clearing output latch
bsf STATUS, RP0 ;Select bank 1
movlw 0xCF ;value used to initialize data direction
movlwf TRISA
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END