COMPUTER
ORGANIZATION AND
ARCHITECTURE
• Prof. (Dr.) Rijwan Khan
• Department of Computer Science and
Engineering
• School of Computing
• Galgotias University, G. B. Nagar
Topics
• Computer System Buses
• Types of the Buses
• Bus Arbitration
• Bus and Memory Transfer
Type of Buses in Computer System
Bus Arbitration
• The device that is allowed to initiate data transfers on the bus at any
given time is called the bus master. In a computer system there may
be more than one bus master such as processor, DMA controller etc.
• They share the system bus. When current master relinquishes control
of the bus, another bus master can acquire the control of the bus.
• Bus arbitration is the process by which the next device to become the
bus master is selected and bus mastership is transferred to it. The
selection of bus master is usually done on the priority basis.
• There are two approaches to bus arbitration: Centralized and
distributed.
1. Centralized Arbitration
• In centralized bus arbitration, a single bus arbiter performs the required
arbitration. The bus arbiter may be the processor or a separate controller
connected to the bus.
• There are three different arbitration schemes that use the centralized bus
arbitration approach. There schemes are:
a. Daisy chaining
b. Polling method
c. Independent request
a) Daisy chaining
The system connections for Daisy chaining method are shown in fig below.
•It is simple and cheaper method. All masters make use of the same line for bus request.
•In response to the bus request the controller sends a bus grant if the bus is free.
•The bus grant signal serially propagates through each master until it encounters the first one that is requesting
access to the bus.
•This master blocks the propagation of the bus grant signal, activates the busy line and gains control of the bus.
•Therefore any other requesting module will not receive the grant signal and hence cannot get the bus access.
b)Polling method
•The system connections for polling method are shown in figure above.
•In this the controller is used to generate the addresses for the master. Number of
address line required depends on the number of master connected in the system.
•For example, if there are 8 masters connected in the system, at least three
address lines are required.
•In response to the bus request controller generates a sequence of master
address. When the requesting master recognizes its address, it activated the busy
line and begins to use the bus.
c)Independent request method:-
•The figure below shows the system connections for the independent request scheme.
•In this scheme each master has a separate pair of bus request and bus grant lines and each pair has a
priority assigned to it.
•The built in priority decoder within the controller selects the highest priority request and asserts the
corresponding bus grant signal.
2. Distributed Arbitration
• In distributed arbitration, all devices participate in the selection of the next bus master.
• In this scheme each device on the bus is assigned a 4-bit identification number.
• The number of devices connected on the bus when one or more devices request for the control
of bus, they assert the start-arbitration signal and place their 4-bit ID numbers on arbitration
lines, ARB0 through ARB3.
• These four arbitration lines are all open-collector. Therefore, more than one device can place
their 4-bit ID number to indicate that they need to control of bus. If one device puts 1 on the
bus line and another device puts 0 on the same bus line, the bus line status will be 0. Device
reads the status of all lines through inverters buffers so device reads bus status 0as logic 1.
Scheme the device having highest ID number has highest priority.
• When two or more devices place their ID number on bus lines then it is necessary to identify
the highest ID number on bus lines then it is necessary to identify the highest ID number from
the status of bus line. Consider that two devices A and B, having ID number 1 and 6,
respectively are requesting the use of the bus.
Bus and Memory Transfers
• A digital system composed of many registers, and paths must
be provided to transfer information from one register to another.
The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and
all other registers in the system.
• A bus structure, on the other hand, is more efficient for
transferring information between registers in a multi-register
configuration system.
• A bus consists of a set of common lines, one for each bit of
register, through which binary information is transferred one at
a time. Control signals determine which register is selected by
the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the help of
four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and
S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected to
input 0 of MUX1.
