CS-336: Embedded Systems
AVR Microcontroller:
Arithmetic Instructions
Slight modification of slides shared by Dr. Rehan Ahmed
Review: Status Register
• All Bits are R/W:
– H – Half Carry Flag
set when there is a carry from D3 to D4 during an ADD or SUB
– S – Sign Bit
XOR of N and V flags
– V – Two’s Complement Overflow Flag
set whenever the signed number result is too large
– N – Negative Flag
N = 0; arithmetic operation result is positive
N = 1; arithmetic operation result is negative
– Z – Zero Flag
If an arithmetic or logic operation result is ZERO
– C – Carry Flag
set whenever there is a carry from the D7 bit
2
Arithmetic
3
UnSigned and Signed Numbers (for humans)
• Unsigned numbers
– all bits represent the magnitude of a positive integer
bn – 1 b1 b0
Magnitude
MSB
• Signed numbers
– left-most bit represents the sign of a number
– And the remaining bits represent the magnitude
bn – 1 bn – 2 b1 b0
Magnitude
Sign
0 denotes + MSB
1 denotes –
4
ALU doesn’t know about Signed/Unsigned
• The ALU just does the binary math and sets the flags
appropriately:
– It's up to you, the programmer, to know which flag to check
after the math is done!
5
Unsigned Arithmetic
6
Addition of Unsigned Numbers
ADD Rd, Rr ; Rd = Rd + Rr
• AVR addition does not support direct memory access:
– Cannot add a memory location to another memory location
or to register
– Operands should first be loaded to any of the GPRs (R0 –
R31)
• ADD instruction could change any of the status flags (i.e.
SREG contents)
7
Machine Code of ADD
ADD Rd, Rr ;Rd = Rd + Rr
• Can you specify the 16-bit machine code for ADD R1,R2 ?
• Answer: Op-code of ADD is 0000 11
• Rd is R1 in this case, so ddddd = 00001.
• Rr is R2 here, so rrrrr = 00010
• Machine code is: 0b 0000 1100 0001 0010
8
ADD instruction
ADD Rd, Rr ;Rd = Rd + Rr ( Direct or immediate are not supported)
Show how the status register (SREG) is affected by the following instructions.
LDI R21,0xF5 ;R21 = F5H
LDI R22,0x0B ;R22 = 0x0BH
ADD R21,R22 ;R21 = R21+R22 = F5+0B = 00 and C = 1
Solution:
F5H 1111 0101
+ 0BH + 0000 1011
100H 0000 0000
After the addition, register R21 contains 00 and the flags are as follows:
C = 1 because there is a carry out from D7.
Z = 1 because the result in destination register (R21) is zero.
H = 1 because there is a carry from D3 to D4.
9
ADD instruction
ADD Rd, Rr ;Rd = Rd + Rr (Direct or immediate are not supported)
Assume that RAM location 400H has the value of 33H. Write a program to find the su
of location 400H of RAM and 55H. At the end of the program, R21 should contain the
Solution:
LDS R2,0x400 ;R2 = 33H (location 0x400 of RAM)
LDI R21,0x55 ;R21 = 55
ADD R21,R2 ;R21 = R21 + R2 = 55H + 33H = 88H, C = 0
10
ADC instructions: Addition of 16-bit Numbers
1
3C
+3B
+3B
E7 8D
78 74
Write a program to add two 16-bit numbers. The numbers are 3CE7H and 3B8DH.
Place the sum in R3 and R4; R3 should have the lower byte.
Solution:
LDI R1, 0x8D ;R2:R1 = 3B 8D
LDI R2, 0x3B
LDI R3, 0xE7 ;R4:R3 = 3C E7
LDI R4, 0x3C
ADD R3,R1 ;R3 = R3 + R1 = E7 + 8D = 74 and C = 1
ADC R4,R2 ;R4 = R4 + R2 + carry, adding the upper byte
;with carry from lower byte
;R4 = 3C + 3B + 1 = 78H (all in hex)
Notice the use of ADD for the lower byte and ADC for the higher byte.
11
Subtraction
Micro-processor performs subtraction with digital circuits already
designed for addition
A B A (B)
Recall, Two's Complement numbers:
B B 1
(Invert all bits of B and add 1 to LSB)
A B A + (2’s Compliment
B)
Steps for Subtraction
12
SUB instructions
SUB Rd, Rr ; Rd = Rd – Rr (immediate values are not
supported)
SUBI Rd, K ; Rd = Rd – K
Show the steps involved in the following.
LDI R20, 0x23 ;load 23H into R20
LDI R21, 0x3F ;load 3FH into R21
SUB R21, R20 ;R21 <= R21-R20
Solution:
R21 = 3F 0011 1111 0011 1111
- R20 = 23 0010 0011 + 1101 1101 (2’s complement)
0 1C 1 0001 1100
C = 0, D7 = N = 0 (result is positive)
The flags would be set as follows: N = 0, C = 0. (Notice that there is a carry but C = 0
See next slide.)
The programmer must look at the N (or C) flag to determine if the result is positive or n
13
Subtraction: Key Take-Aways
• In AVR, the CPU inverts the C flag after the SUB
instruction,
– Notice that the CPU does not invert the carry flag after the
ADD instruction
– If C=0 (N=0), the result is positive
– If C=1 (N=1), the result is negative
Destination will have the result in 2’s complement form
Use NEG to change the result back to normal
14
SUBI- Subtract Immediate
SUBI Rd, K ;Rd = Rd – K 16 ≤ d ≤ 31,
15
SBIW- Subtract Immediate from Word
SBIW Rd+1:Rd, K ;Rd+1:Rd = Rd – K
operates on the upper four register pairs only
K=(0,63)
16
SBIW: Details and Op-code
SBIW Rd+1:Rd, K ;Rd+1:Rd = Rd – K
Note the limitations
on the choice of Rd
as well as K !
17
SBC instruction
SBC Rd, Rr ;Rd = Rd – Rr – C ( immediate are not supported)
SBCI Rd, K ;Rd = Rd – K – C
28 62 (H)
- 12 96 (H)
---------------
15 CC (H)
;R26 <= 62(H) ;R28 <= 96(H)
;R27 <= 28(H) ;R29 <= 12(H)
SUB R26, R28 ;R26 = R26 - R28 = 62 - 96 = CC(H) while
;C = borrow = 1, N = 1
SBC R27, R29 ;R27 = R27 – R29 – C
;R27 = 28 – 12 – 1 = 15(H)
After the SUB, R26 has 62(H) – 96(H) = CC(H) and the carry flag is set to 1,
indicating there is a borrow (notice, N = 1).
Because C = 1, after SBC is executed then R27 has 28(H) – 12(H) - 1 = 15H.
Therefore, we have 2862(H) – 1296(H) = 15CC(H).
18
Use of SBC for Multibyte Subtraction
SBC Rd, Rr ; Rd <= Rd – Rr - C
Already done !
19
Multiplication
Multiplication: performs 8-bit × 8-bit → 16-bit multiplication.
MUL Rd,Rr ; R1:R0 = Rd × Rr (Multiply Unsigned)
MULS Rd,Rr ; R1:R0 = Rd × Rr (Multiply signed)
MULSU Rd,Rr ; R1:R0 = Rd × Rr (Multiply signed with
unsigned)
Result of
multiplication is
placed in R1 and R0
registers !
20
Division
• AVR has no instruction for division:
– implemented by repeated subtraction
Numerator is placed in a register and the denominator is
subtracted from it repeatedly
The quotient is the number of times we subtract
Remainder is in the register upon completion
.DEF NUM = R20
.DEF DENOMINATOR = R21
.DEF QUOTIENT = R22
LDI NUM,95 ;NUM = 95
LDI DENOMINATOR,10 ;DENOMINATOR = 10
CLR QUOTIENT ;QUOTIENT = 0
LOOP: INC QUOTIENT
SUB NUM, DENOMINATOR
BRCC LOOP ;branch if C (borrow) is zero
DEC QUOTIENT ;SUB done once too many
ADD NUM, DENOMINATOR ;add back to it
21
Signed Arithmetic
22
Signed Number
D7 D6 D5 D4 D3 D2 D1 D0
sign magnitude
Note: N flag in SREG is actually the value of D7 bit !
Range is decreased to 0 to +127 for +ive number
23
Representation of Negative Numbers
• Negative numbers can be represented in three different
ways:
1. Sign and magnitude
2. 1’s complement
3. 2’s complement
24
Overall: Interpretation of 4-bit
Signed Numbers
25
Byte-sized Negative Numbers
AVR assembler converts the negative number to its 2’s
complement representation.
26
Overflow Flag V
• In 8 bit signed arithmetic, Vis set to 1 if:
– Carry from D6 to D7, but not from D7 to out
– Carry from D7 to out but no carry from D6 to D7
– ADD with same signs, Overflow happens
– ADD with same sign, result must have same sign, if
different, it means error
– See next example
27
Overflow problem: Example
ndicates error by raising V flag, it is up to programmer to take care of erroneous
S – Sign Bit
XOR of N and V flags
28
Example
S – Sign Bit
XOR of N and V flags
29
Example
1111
1011
S – Sign Bit
XOR of N and V flags
30
Example
31
Lessons to Remember
32
Important Take-away – (1)
• If your program treats the bits in a word as unsigned
numbers:
– you must watch to see if your arithmetic sets the carry flag
(C) on, indicating the result is wrong.
– You don't care about the overflow flag when doing unsigned
math.
The overflow flag is only relevant to signed numbers, not
unsigned!
33
Important Take-away – (2)
• If your program treats the bits in a word as two's
complement signed values:
– you must watch to see if your arithmetic sets the overflow
(V) flag on, indicating the result is wrong.
– You don't care about the carry flag when doing signed, two's
complement math.
The carry flag is only relevant to unsigned numbers, not
signed!
34
Sum-up: C vs V Flags
• In unsigned arithmetic, watch the carry flag to detect
errors:
– In unsigned arithmetic, the overflow flag does NOT tell you
anything interesting.
• In signed arithmetic, watch the overflow flag to detect
errors:
– In signed arithmetic, the carry flag does NOT tell you
anything interesting.
35
Carry Flag (C): When is it set?
• There are two rules for turning on the carry flag in
binary/integer math:
1. The carry flag is set if the addition of two numbers causes
a carry out of the most significant (leftmost) bits added.
1111 + 0001 = 0000 (carry flag is turned on)
2. The carry (borrow) flag is also set if the subtraction of two
numbers requires a borrow into the most significant
(leftmost) bits subtracted.
0000 - 0001 = 1111 (carry flag is turned on)
• Otherwise, the carry flag is turned off (zero).
* 0111 + 0001 = 1000 (carry flag is turned off [zero])
* 1000 0001 = 0111 (carry flag is turned off [zero])
36
Overflow Flag (V): When is it set?
• There are two rules for turning on the overflow flag in
binary/integer math :
1. If the sum of two numbers with the sign bits off yields a
result number with the sign bit on, the "overflow" flag is
turned on.
0100 + 0100 = 1000 (overflow flag is turned on)
2. If the sum of two numbers with the sign bits on yields a
result number with the sign bit off, the "overflow" flag is
turned on.
1000 + 1000 = 0000 (overflow flag is turned on)
• Otherwise, the overflow flag is turned off.
– 0100 + 0001 = 0101 (overflow flag is turned off)
– 0110 + 1001 = 1111 (overflow flag is turned off)
– 1000 + 0001 = 1001 (overflow flag is turned off)
– 1100 + 1100 = 1000 (overflow flag is turned off) 37
Difference between N and S flags
• N = D7 – Negative Flag
– N = 0; arithmetic operation result is positive
– N = 1; arithmetic operation result is negative
• S – Sign Bit
– XOR of N and V flags
• Overflow corrupts the result and negates the sign bit:
– If adding two positive numbers sets V, the N flag would be 1
as well, showing that the result is negative (which is wrong)
Take a look at the previous example
– When that happens, the S flag helps you to know the sign of
the real result
38
Reading
• The AVR Microcontroller and Embedded Systems: Using
Assembly and C by Mazidi et al., Prentice Hall
– Chapter-5: 5.1 and 5.2
• Also perform the code examples to enhance your
understanding.
39
THANK YOU
