Architecture of 8085

Different Blocks
• The internal architecture of 8085 includes
1. Arithmetic Logic Unit (ALU) Section
2. Register Section
3. The Timing and Control Unit Section
4. The Interrupt Control Section

5. Serial I/O Control Section

All Block are connected across an 8-bit data Bus.

Power +5 V
Supply GND
 Arithmetic & Logic Section
• This section consists of :

• Arithmetic Logic Unit (ALU)

• Accumulator (A)

• Temporary Register (TR)

• Flag Register / Flag Flip-Flops(F)

 Internal Data Bus (8)

Temp. (8)
Flags
Flip-Flops (5)
Accumulator
A (8)

ALU (8)
(8)

: Control Signals
 Arithmetic Logic Unit (ALU)
• Consists of arithmetic and logic circuits
• Operates on the two operands stored in
• Accumulator
• Temporary register
• The result is stored in Accumulator
• Governed by control signals generated by control unit.
•It can perform
 Binary addition, subtraction, increment and decrement,
 Logical AND, OR and EX-OR,
 Complement,
 Rotate left or right.
 Some points to note
• During subtraction the content of temporary register is subtracted from the Accumulator.

Example1 :
SUB B : Subtract the content of register B from A
The content of B is copied to temp register and subtraction is performed.

Example2 :
SUB M : Subtract the content of specified memory location from A
The content of memory location is copied to temp register and subtraction is performed.

• The ALU contains additional logic circuit to adjust the result of addition operations During BCD
addition.
• An instruction 'DAA’ uses the circuit to adjust the result to BCD form.
 Accumulator & Temp register
•Accumulator
•Accumulator (A) is a special purpose register
1. Holds the 1st operands in arithmetic and logical instructions

2. Store the result after arithmetic and logical operations

•Temp Register
1. Not accessible to programmer i.e. can not be read or write directly or indirectly by
any instruction.
2. The second operand in a register or memory is transferred to Temp register before
performing the arithmetic and logical operations.
 Flag Register/Flip-Flops
• 5 flags are used to store the status of results after execution of any arithmetic
and logical operations.
• Some instruction for increment and decrement are excluded
• Reflects the data condition
• The status value is used in taking certain decision.
 Flag Register

S Z - AC - P - CY

S : Sign Flag
S: Sign Flag
S=1: when result is Negative (signed Arithmetic)
Z: Zero Flag
S=0: when result is negative (signed Arithmetic)
AC: Auxiliary Flag
• Copy the D7 bit of Result
P: Parity Flag
• Used in Signed Arithmetic
Cy: Carry Flag
 Flag Register

S Z AC P CY

Z : Zero Flag
S: Sign Flag
Z=1: If result is Zero
Z: Zero Flag Z=0: 0 when result is Non-zero
AC: Auxiliary Flag
AC: Auxiliary Flag
P: Parity Flag Ac=1: when a carry generated from lower nibble to higher nibble
Cy: Carry Flag Carry from to
AC=0: otherwise
Used in BCD arithmetic to change the result to BCD form
 Flag Register

S Z AC P CY

S: Sign Flag P: Parity Flag (ODD Parity)

P=1: even no of 1 in the result (least 8-bit)
Z: Zero Flag
P=0: Odd no of 1 in the result (least 8-bit)
AC: Auxiliary Flag
P: Parity Flag CY: Carry Flag
CY=1, when a carry from bit during addition or borrow to bit in
Cy: Carry Flag subtraction
CY=0: Otherwise
 Example-1 : Addition
Upper Nibble Lower Nibble
AC
1 1

DA H 1 1 0 1 1 0 1 0
60 H
+ 0 1 1 0 0 0 0 0
1 3A H 1 0 0 1 1 1 0 1 0
Carry
S 0 As
Z 0 Result is not Zero
AC 0 Carry from (Lower to Higher Nibble)
P 1 Odd number (4 bits) of bits are 1
CY 1 Carry generated from
 Example-2 : Addition
ok
Upper Nibble Lower Nibble
AC
1 1 1 1 1 1 1 1

BB H 1 0 1 1 1 0 1 1
45 H + 0 1 0 0 0 1 0 1
1 00 H 1 0 0 0 0 0 0 0 0
Carry
S 0 As
Z 1 Result is Zero
AC 1 Carry from (Lower to Higher Nibble)
P 1 EVEN number (None) of bits are 1
CY 1 Carry from
 Example-3 : Subtraction
ok
Upper Nibble Lower Nibble
Borrow AC
1 1 1 1 1 1 1 1

B4H 1 0 1 1 0 1 0 0
B5 H ̶ 1 0 1 1 0 1 0 1
1 3A H 1 1 1 1 1 1 1 1

S 1 As
Z 0 Result is not Zero
AC 1 Borrow from (Higher to Lower Nibble)
P 1 EVEN number (8 bits) of bits are 1
CY 1 B
 Example-4 : Subtraction
Upper Nibble Lower Nibble

Borrow AC
1 1 1

B4 H 1 0 1 1 0 1 0 0
CC H ̶ 1 1 0 0 1 1 0 0
Borrow
E8 H 1 1 1 0 1 0 0 0

S 1 As
Z 0 Result is not Zero
AC 1 Borrow from (Higher to Lower Nibble)
P 1 Even number (4-bits) of bits are 1
CY 1 B
8085 Microprocessor has following types of registers.
1. General Purpose Register
• These registers are used to store data or address temporarily inside the processor.
Generally the registers are used to store
• The result,
• Data to be processed,
• Address of data to be read and processed,
• Address of the result to be stored.
2. Special Purpose Register
These registers are used for some specific purpose and not used to store temporary
data or address.
3. Temporary Registers
These registers are used by the processor for its internal operation. These registers are
directly or indirectly not accessible by the programmer (no instruction use this
registers).
 General Purpose Register

• Six 8-bit general purpose registers are available in 8085. They are represented as
B, C, D, E, H, L
• They can be used in pair to store16-bit data or address. The three registers pairs
formed are represented as

Register Pairs 16-bit name

BC B B (8) C (8) B (16)
DE D D (8) E (8) D (16)
HL H H (8) L (8) H (16)

Whether the register is 16-bit or 8-bit is identified from the instruction.

 Special Purpose Register
1. Program Counter (PC) : 16-bit
• This is a 16-bit register used to holds the address of the next instruction to be fetched.
• After fetching the current instruction, the register is incremented by the processor to point
the next instruction.
2. Stack Pointer (SP) : 16-bit
• It is a 16-bit register.
• It holds the address of top of the stack.
• Automatically it is decremented by two by the processor after a PUSH operation (writing data
to stack).
• Automatically it is incremented by two by the processor after a POP operation (reading data
from stack).
• Thus it always points to the top of the stack.
 Special Purpose Register
• Accumulator and Flag register : 8-bit
• The registers are present in ALU unit.
• They form a pair for PUSH and POP operation.

PUSH : Writing data to Stack

POP : Reading data from stack

Stack Operations are always two bytes. So, register pair

are pushed or popped as required.
 Special Purpose Register
• The incrementer/decrementer : 16-bit
• used for multiple purposes
• increments the program counter as instructions execute
• increments and decrements the stack pointer as needed
• supports the 16-bit increment and decrement instructions to increment
any register pair(B, D, H).
• Address Latch : 16-bit
• It holds the address of memory or IO that will be fetched next.
• It loads the address to address bus through buffer registers.
• Address /data buffer and address buffer
• They drive the Address and data bus.
• The address data buffer also send and receive data from internal data bus.
 Temporary Register
• Temp register: 8-bit
• Available in ALU section.
• The second operand is copied to the TEMP register to feed to Accumulator.
• WZ-Register : 8-bit
• Temporary registers W and Z are 8-bit register and also used in pair when
necessary.
• This temporary register is used by the microprocessor and it is completely
inaccessible to programmers.
• These registers are used by the processor to hold operand, intermediate
operand, and address of memory and I/O devices temporarily.
• Also used by processor in execution of certain instructions.
 Special Purpose Register
• Instruction Register (IR) : 8-bit
• An 8-bit register that holds the opcode fetched (1st byte of any instruction).
• Opcode : Operation code
• Instruction Decoder and M/C Encoder
• This block reads the opcode from IR and decode it.
• It also determine the Machine cycle required to complete the execution of the
instruction.
• The decoded information are fed to Control and Timing unit to generate necessary
control signals.
 Internal Data Bus (8)

MUX
Instruction Register W (8) Z (8)

Register Select
(8)
B (8) C (8)
D (8) E (8)
H (8) L (8) A(8) Flag (8) PSW(16)
Instruction Decoder
SP (16)
&
Machine Cycle PC (16) Only for PUSH and POP
Encoding Incrementer/Decrementer operations
Address Latch (16)

To Control Unit
Address Buffer Address Data Buffer
Address Bus (Upper Byte) 𝐴15 − 𝐴8𝐴𝐷 7 − 𝐴𝐷 0 Address /Data bus
 Timing and Control Unit
• Generates control and timing signal
• To synchronize and control internal and external devices
• The oscillator lies in this section. X1 and X2 pin are used to connect a crystal
or a RC- or LC-Circuit.
• The Clock-out signal is available to synchronize external devices.
• It also generates
• Control Signals: , ,
• Status Signals:
• DMA Signals:
• RESET Signals: ,
 Timing and Control Unit
𝑋1
𝑋2
Clock Gen Control Status Reset DMA

Clock Out 𝑅𝐷 𝑊𝑅𝐴𝐿𝐸 𝑆 0𝑆 1𝐼𝑂/ 𝑀 𝑅𝐸𝑆𝐸𝑇 𝑂𝑈𝑇 𝐻𝐿𝐷𝐴

𝑅𝐸𝐴𝐷𝑌 𝑅𝐸𝑆𝐸𝑇 𝐼𝑁 𝐻𝑂𝐿𝐷

Control Signals: ,,
Status Signals:
DMA Signals:
RESET Signals: ,
 Interrupt Control Section
• This section has 5 hardware interrupt input and one interrupt acknowledge output ().
1. : Non-maskable vectored interrupt
2. : Maskable and vectored
3. : Maskable and vectored
4. : Maskable and vectored
5. : Maskable and Non-vectored
• It recognizes the external interrupt (if any).
• Encode vector address (if any) to transfer the control to ISR (Interrupt Service
Routine).
• Generates signal when INTR interrupt is recognized.
• Used to enable, disable or mask some interrupts
𝑰𝑵𝑻𝑨 𝑰𝑵𝑻𝑹 𝑹𝑺𝑻 𝟓.𝟓 𝑹𝑺𝑻 𝟔.𝟓 𝑹𝑺𝑻 𝟕.𝟓 𝑻𝑹𝑨𝑷

Interrupt Controller
 Serial I/O control section
• Control the serial communication.
• The serial input () and serial output () lines are connected to this section.
𝑺𝑶𝑫 𝑺𝑰𝑫

Serial IO Controller