ARM Memory
Organisation
ARM Memory Model
• ARM IS addresses upto 4GB address space of 232 bytes or 230 word or 231 half word.
• The architecture provides facilities for:
• generating an exception on an unaligned memory access
• restricting access by applications to specified areas of memory
• translating virtual addresses provided by executing instructions into physical
addresses
• altering the interpretation of word and halfword data between big-endian and
little-endian
• controlling the order of accesses to memory
• controlling caches
• synchronizing access to shared memory by multiple processors.
15/12/2024 Zaikenn Technologies 2
Memory Types
• Each defined memory region will specify a memory type
• The memory type controls the following:
• Memory access ordering rules
• Caching and buffering behaviour
• There are 3 mutually exclusive memory types:
• Normal
• Device
• Strongly Ordered
• Normal and Device memory allow additional attributes for specifying
• The cache policy
• Whether the region is Shared
• Normal memory allows you to separately configure Inner and Outer cache policies
15/12/2024 3
ARM Memory Model
15/12/2024 5
In an ARM processor, cache memory is a small, fast block of memory that stores
copies of recently accessed data from the main memory.
Cache memory is located between the processor core and main memory, and is
typically integrated with the CPU cores on the same chip.
Cache memory is faster than main memory because it has a higher bandwidth, lower
latency, and a dedicated connection between the CPU and cache.
The goal of cache memory is to reduce the memory access bottleneck imposed on
the processor core by slow memory.
Cache memory is categorized into three general levels:
•L1 cache: Also known as primary cache, this is extremely fast but relatively small.
•L2 cache: This is often more capacious than L1.
•Level 3 (L3) cache: This is specialized memory developed to improve the
performance of L1 and L2.
ARM Cache Memory
System
I-Cache RAM L2 Cache
MMU/MPU
Off-chip
ARM Core Memory
On-chip
BIU
SRAM
D-Cache RAM
L1 L2 L3
• Typical memory system can have multiple levels of cache
• Level 1 memory system typically consists of L1-caches, MMU/MPU and TCMs
• Level 2 memory system (and beyond) depends on the system design
15/12/2024 7
