Operating
Systems:
Internals
and
Chapter 1
Design Computer
Principles
System Overview
Eighth Edition
Global Edition
By William Stallings
Operating System
Exploits
the hardware resources of one or
more processors
Provides a set of services to system users
Manages secondary memory and I/O
devices
Basic Elements
Process I/O
or Modules
Main System
Memory Bus
Processor
Performs the
Controls the
data
operation of
processing
the computer
functions
Referred to as
the Central
Processing
Unit (CPU)
Main Memory
Volatile
Contentsof the memory is
lost when the computer is
shut down
Referredto as real memory
or primary memory
I/O Modules
storage (e.g.
hard drive)
Moves data
between the
computer and communicatio
external ns equipment
environments
such as:
terminals
System Bus
Provides
for
communication among
processors, main
memory, and I/O
modules
Microprocessor
Invention
that brought about
desktop and handheld computing
Processor on a single chip
Fastest general purpose processor
Multiprocessors
Eachchip (socket) contains multiple
processors (cores)
Graphical Processing
Units (GPU’s)
Provide efficient computation on
arrays of data using Single-
Instruction Multiple Data (SIMD)
techniques
Used for general numerical
processing
Physics simulations for games
Computations on large spreadsheets
Digital Signal
Processors
(DSPs)
Deal with streaming signals such
as audio or video
Used to be embedded in devices
like modems
Encoding/decoding speech and
video (codecs)
Support for encryption and security
System on a Chip
(SoC)
To
satisfy the requirements of
handheld devices, the
microprocessor is giving way to the
SoC
Components such as DSPs, GPUs,
codecs and main memory, in
addition to the CPUs and
caches, are on the same chip
Instruction Execution
A program consists of a set of
instructions stored in memory
processor reads
processor
(fetches)
executes each
instructions from
instruction
memory
Two steps
Instruction Fetch
and Execute
Theprocessor fetches the instruction
from memory
Program counter (PC) holds address of
the instruction to be fetched next
PC is incremented after each fetch
Instruction Register
(IR)
Processor interprets
Fetched instruction is
loaded into the instruction and
Instruction Register performs required
(IR) action:
Processor-
memory
Processor-I/O
Data processing
Control
Interrupts
Interrupt
the normal sequencing of the
processor
Provided to improve processor
utilization
most I/O devices are slower than the processor
processor must pause to wait for device
wasteful use of the processor
Table 1.1 Classes of Interrupts
Program Generated by some condition that occurs as a result of
an instruction execution, such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, and
reference outside a user's allowed memory space.
Timer Generated by a timer within the processor. This allows the
operating system to perform certain functions on a
regular basis.
I/O Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of
error conditions.
Hardware Generated by a failure, such as power failure or
memory
failure parity error.
Figure 1.5a
Flow of Control
Without
Interrupts
Figure 1.5b
Short I/O Wait
Figure 1.5c
Long I/O Wait
Multiple Interrupts
An interrupt occurs
while another
Two approaches:
interrupt is being
processed
• e.g. receiving data • disable interrupts
from a while an interrupt is
communications being processed
line and printing • use a priority
results at the same scheme
time
Memory Hierarchy
Major constraints in memory
amount
speed
expense (cost)
Memory must be able to keep up with the
processor
Cost of memory must be reasonable in
relationship to the other components
Memory Relationships
Faster Greater
access capacity =
time = smaller cost per
greater bit Greater
cost per capacity =
bit slower access
speed
The Memory Hierarchy
Going down the
hierarchy:
decreasing cost per
bit
increasing capacity
increasing access time
decreasing frequency
of access to the
memory by the
Cache Memory
Invisible to the OS
Interacts with other memory management hardware
Processor must access memory at least once per
instruction cycle (Processor is faster than memory)
Processor execution is limited by memory cycle time
Exploit the principle of locality with a small, fast
memory which contains a portion of main memory
C<<M
Cach
e cache
size
Desig number
block
of cache
n levels
size
Main
categori
es are:
write mapping
policy function
replacem
ent
algorithm
Cache and Block Size
Cache Block
Size Size
the unit of data
small caches
exchanged
have significant
between cache
impact on
and main
performance
memory
Mapping Function
∗ Determines which
cache location the block
will occupy when one block is
read in, another may
have to be replaced
Two constraints affect
design:
the more flexible the
mapping function, the
more complex is the
circuitry required to
search the cache
Replacement Algorithm
Least Recently Used (LRU)
Algorithm
effective strategy is to replace a block that
has been in the cache the longest with no
references to it
hardware mechanisms are needed to
chooses
identify thewhich
leastblock to replace
recently usedwhen a new
block
block is to be loaded into the cache
Write Policy
Dictates when the memory write operation
takes place
• can occur every time the block is updated
• can occur when the block is replaced
• minimizes write operations
• leaves main memory in an obsolete state
I/O Techniques
∗When the processor encounters an instruction
relating to I/O, it executes that instruction by
issuing a command to the appropriate I/O
module
Three techniques are possible for I/O
operations:
Direct
Programme Interrupt-
Memory
d I/O Driven I/O
Access (DMA)
Programmed I/O
The I/O module performs the requested
action then sets the appropriate bits in the
I/O status register
The processor periodically checks the
status of the I/O module until it determines
the instruction is complete
With programmed I/O the performance
level of the entire system is severely
degraded
Interrupt-Driven I/O
Processor
issues an
I/O The
command processor
to a module executes the
and then data transfer
goes on to and then
do some resumes its
other useful former
work processing
The I/O module More efficient than
will then interrupt Programmed I/O
the processor to but still requires
request service active intervention
when it is ready to of the processor to
exchange data transfer data
with the processor between memory
and an I/O module
Interrupt-Driven I/O
Drawbacks
Transferrate is limited by the speed
with which the processor can test and
service a device
The processor is tied up in managing
an I/O transfer
a number of instructions must be
executed for each I/O transfer
Direct Memory Access
(DMA)
∗ Performed by a separate module on the system
bus or incorporated into an I/O module
When the processor wishes to read or write
data it issues a command to the DMA module
containing:
• whether a read or write is requested
• the address of the I/O device involved
• the starting location in memory to read/write
• the number of words to be read/written
Direct Memory Access
Transfers the entire block of data
directly to and from memory without
going through the processor
processor is involved only at the beginning and
end of the transfer
processor executes more slowly during a transfer
when processor access to the bus is required
Moreefficient than interrupt-driven or
programmed I/O
Multicore Computer
Also known as a chip multiprocessor
Combines two or more processors
(cores) on a single piece of silicon (die)
each core consists of all of the
components of an independent processor
Inaddition, multicore chips also
include L2 cache and in some cases L3
cache
Summary
Basic Elements Cache memory
Evolution of the Motivation
microprocessor Cache principles
Instruction execution
Cache design
Interrupts
Direct memory access
Interrupts and the Multiprocessor and
instruction cycle multicore organization
Interrupt processing Symmetric
Multiple interrupts multiprocessors
The memory hierarchy Multicore computers
