LECTURE 1
VLSI
&
Introduction of CMOS
LIST OF COURSE TOPICS
Introduction to VLSI Systems
CMOS logic, fabrication and layout
MOS transistors, Different types of
inverter,
Circuit characterization and
performance estimation
Circuit Simulation
Combinational and sequential circuit design
Memory system design
Design methodology and tools
EVOLUTION OF INTEGRATION LEVEL IN INTEGRATED
CIRCUIT
INTRODUCTION TO VLSI SYSTEMS
VLSI Design - Digital System. Very-large-scale integration (VLSI) is the process of
creating an integrated circuit (IC) by combining thousands of transistors into a
single chip.
VLSI began in the 1970s when complex semiconductor and communication
technologies were being developed. The microprocessor is a VLSI device .
VLSI circuits are used everywhere, real applications include microprocessors in a
personal computer or workstation, chips in a graphic card, digital camera or
camcorder, chips in a cell phone or a portable computing device, and embedded
processors in an automobile
Reduces the size of circuits.
Reduces the effective cost of the devices.
Increases the operating speed of circuits.
Requires less power than discrete components.
VLSI DESIGN: OVERVIEW
VLSI design is system design
Designing fast inverters is fun, but need knowledge of all
aspects of digital design: algorithms, systems, circuits,
fabrication, and packaging
Need to bridge gap between abstract vision of digital design
and the underlying digital circuit and its peculiarities
Circuit-level optimization, verification, and testing techniques
are important
VLSI: ENABLING TECHNOLOGY
Automotive electronic systems
A typical car has over 100 ICs (stereo systems, display panels, fuel
injection systems, smart suspensions, antilock brakes, airbags)
Signal Processing (digital signal processor (DSP) chips, data acquisition
systems)
Transaction processing (bank ATMs)
PCs, workstations, servers, consumer electronics
Medical electronics (artificial eye, implants)
Space applications
Networking hardware: Routers and switches
VLSI TECHNOLOGY
CMOS: Complementary Metal Oxide Silicon
Based on voltage-controlled field-effect transistors (FETs)
Other technologies: bipolar junction transistors (BJTs), BiCMOS, gallium
arsenide (GaAs)
BJTs, BiCMOS, ECL circuits are faster but CMOS consumes lower power
and are easier to fabricate
GaAs carriers have higher mobility but high integration levels are difficult
to achieve in GaAs technology
VLSI TECHNOLOGY
Bipolar transistors: the controlled current must go through two types of
semiconductor material: P and N.
3 terminals are named base, collector and emitter.
A base current turns the transistor on like a closed switch and allows a
proportional amount of current through the collector.
npn or pnp silicon “sandwich” structure
Small current into very thin base layer
controls large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
IC TECHNOLOGY
MAKING MICROCHIP
Making wafers: We grow pure
silicon crystals into long
cylinders and slice them (like
salami) into thin wafers, each of
which will ultimately be cut up
into many chips.
Masking: We heat the wafers to
coat them in silicon dioxide and
use ultraviolet light (blue) to
add a hard, protective layer
called photoresist.
Etching: We use a chemical to
remove some of the photoresist,
making a kind of template
pattern showing where we want
areas of n-type and p-type
silicon.
MAKING MICROCHIP
Doping: We heat the etched
wafers with gases containing
impurities to make the areas of
n-type and p-type silicon. More
masking and etching may
follow.
Testing: Long metal connection
leads run from a computer-
controlled testing machine to the
terminals on each chip. Any
chips that don't work are marked
and rejected.
Packaging: All the chips that
work OK are cut out of the
wafer and packaged into
protective lumps of plastic,
ready for use in computers and
other electronic equipment.
DIGITAL CHIP
A digital integrated circuit, (digital chip)
a digital logic circuit or system that integrates
components and connections on the same
semiconductor chip.
designed to use digital logic (Boolean algebra) to
process digital signals, which are discontinuous or
binary.
the basis for all computing operations and are
essential for programmable devices, microcontrollers,
logic boards, and memory
A good VLSI design system should provide
all three description domains (behavioral, structural, and
physical) and
at all relevant levels of abstraction (e.g., architecture,
RTL/block, logic, and circuit).
Y-CHA
The behavioral domain
specifies what we wish
to accomplish with a
system.
The structural domain
specifies the
interconnection of
components required to
achieve the behavior
the physical domain
specifies how to
arrange the
components in order to
connect them,
TOP-DOWN/BOTTOM UP
HOW TO MAKE A (DIGITAL) CHIP
What is the basic design abstraction
• Architectural or functional level
• Circuit level
• Logic or Register Transfer Level (RTL)
Follow the steps
Design Optimization
Optimization of
–Area
– Speed
– Power dissipation
– Reliability
– Testability
– Design time
BOTTOM-UP
DESIGN TOP-DOWN DESIGN
Start with smallest detail Start design from overall
and build up to highest description and end
abstraction design with smallest
– Design individual detail
transistors – specification
– Combine transistors into – architecture
gates – logic design
– Defining own cell library – circuit design
• Schematic
– physical layout
• Symbol
• Layout
Verify at each level of
– Build larger circuits with abstraction
cell libraries
TOP-DOWN DESIGN
Specification (Words): function, interface,
cost, performance, etc.
Architecture (Drawing, Simulation): large
blocks, system level view
Logic (Schematic, Simulation): gates +
registers
Circuits (Schematic, Simulation): transistor
sized for speed, power, area
Layout: Custom or existing library
Extracted Layout (Simulation)
SPECIFICATION
Setting Specifications
– Agreeing with other designers what the interface
is
– Customer interviews
– Comparison with competitors
Good Requirements
– Correct
– Unambiguous
– Complete
– Verifiable
– Consistent: do not contradict
– Modifiable: can update
ARCHITECT
Divide and conquer
Verify by simulating
Hardware Description Languages (HDL)
– Coded functional descriptions that can be mapped
into hardware
Two popular HDLs
– VHDL: higher-level language, describes function at
the “behavioral” level
– Verilog: can describe circuit at behavioral level down
to the transistor level. syntax similar to a C program
Use
– good for designing/simulating complex circuits before
committing to physical design (layout)
– only good for digital/logic circuits, not anal
ARCHITECT →LOGIC DESIGN
Example VHDL Code
2-to-4 Decoder
Logic Synthesis
– Tool: Synopsys Design
Vision
– Input: 1) Circuit described
in an HDL
2) Logic cell library
– Output: A Verilog file
describing a function (circuit)
with logic cells from the
library
TOP-DOWN DESIGN
Introduction to CMOS
INTRODUCTION
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
P-N JUNCTIONS
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
SILICON LATTICE
Transistors are built on a silicon substrate Si Si Si
Silicon is a Group IV material
Si Si Si
Forms crystal lattice with bonds to four neighbors
Si Si Si
DOPANTS
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si
Si Si Si Si Si Si
NMOS TRANSISTOR
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS)
capacitor
Even though gate is no longer made of metal*
Source Gate Drain
Polysilicon
SiO2
n+ n+
Body
p bulk Si
NMOS OPERATION
Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2
0
n+ n+
S D
p bulk Si
NMOS OPERATION CONT.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2
1
n+ n+
S D
p bulk Si
NMOS AND PMOS
nMOS is (built on a p-type substrate) with n-type source and drain diffused on
it. In nMOS, the majority carriers are electrons.
When a high voltage is applied to the gate, the nMOS will conduct.
Similarly, when a low voltage is applied to the gate, nMOS will not conduct.
nMOS are considered to be faster than PMOS, since the carriers in nMOS,
which are electrons, travel twice as fast as the holes.
pMOS consists P-type Source and Drain diffused on an N-type substrate.
Majority carriers are holes.
When a high voltage is applied to the gate, the pMOS will not conduct.
When a low voltage is applied to the gate, the pMOS will conduct.
The PMOS devices are more immune to noise than NMOS devices.
PMOS TRANSISTOR
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2
p+ p+
n bulk Si
TRANSISTORS AS SWITCHES
We can view MOS transistors as electrically controlled
switches
Voltage at gate, controls path from source to drain
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
CMOS
"Complementary Metal Oxide Semiconductor." It is a
technology used to produce integrated circuits.
The "MOS" in CMOS, Transistor operation is controlled
by electric fields, called MOSFETs (metal oxide
semiconductor field-effect transistors).
The "complimentary" part of CMOS refers to the two
different types of semiconductors each transistor
contains — N-type and P-type.
N-type semiconductors have a greater concentration of
electrons than holes, or places where an electron could
exist.
P-type semiconductors have a greater concentration of
holes than electrons.
The CMOS basic block works as an inverter. i.e a NOT
gate.
When input is low output is high and vice versa
CMOS INVERTER
The inverter circuit as shown in the figure below. It consists of pMOS and
nMOS FET. The input A serves as the gate voltage for both transistors.
LOGIC LOGIC
INPUT OUTPUT
INPUT OUTPUT
0v 0 Vdd 1
Vdd 1 0v 0
The nMOS transistor has an input from Vss (ground) and pMOS transistor has
an input from Vdd. The terminal Y is output. When a high voltage (~ Vdd) is
given at input terminal (A) of the inverter, the pMOS becomes open circuit
and NMOS switched ON so the output will be pulled down to Vss.
When a low-level voltage (<Vdd, ~0v) applied to the inverter,
the NMOS switched OFF and PMOS switched ON. So the output
becomes Vdd or the circuit is pulled up to Vdd.
CMOS INVERTER
A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF
A Y
GND
CMOS NAND GATE
The below figure shows a 2-input Complementary MOS NAND gate. It
consists of two series NMOS transistors between Y and Ground and two
parallel PMOS transistors between Y and VDD.
Pull-Down Pull-up OUTPUT
A B
Network Network Y
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0
If either input A or B is logic 0, at least one of the NMOS transistors will be
OFF, breaking the path from Y to Ground. But at least one of the pMOS
transistors will be ON, creating a path from Y to V DD. Hence, the output Y
will be high.
If both inputs are high, both of the nMOS transistors will be ON and both of
the pMOS transistors will be OFF. Hence, the output Y will be logic low.
The truth table of NAND logic gate given in table.
CMOS NAND GATE
A B Y
0 0 1 ON
OFF
ON
OFF OFF
ON
0 1 1
1
Y
1 0 1 0
A ON
OFF
1 1 0
0
1
1
0
B OFF
ON
ON
OFF
nMOS
pMOS
nMOS
pMOS
3-INPUT NAND GATE
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
Y
A
B
C
CMOS NOR GATE
A 2-input NOR gate is shown in the figure below. The NMOS transistors
are in parallel to pull the output low when either input is high. The PMOS
transistors are in series to pull the output high when both inputs are low, as
given in below table. The output is never left floating.
The truth table of NOR logic gate given in below table.
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
CMOS NOR GATE
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
CMOS ADVANTAGE:
CMOS (complementary metal oxide semiconductor) logic has a few
desirable advantages:
High input impedance. The input signal is driving electrodes with a
layer of insulation (the metal oxide) between them and what they are
controlling. This gives them a small amount of capacitance, but
virtually infinite resistance
The outputs actively drive both ways
The outputs are pretty much rail-to-rail
CMOS logic takes very little power when held in a fixed state. The
current consumption comes from switching as those capacitors are
charged and discharged. Even then, it has good speed to power ratio
compared to other logic types.
CMOS gates are very simple. The basic gate is an inverter, which is
only two transistors. This together with the low power consumption
means it lends itself well to dense integration. Or conversely, you get a
lot of logic for the size, cost and power.
CMOS DIS-ADVANTAGE:
CMOS technology for implementing vision chips the disadvantages are as
follows;
Analog circuit design: Leading edge processes are not characterized and
tuned for analog circuit design.
Photodetectors: The photodetector structures are not characterized in
any of the processes. It is the designer’s responsibility to assure that the
photodetectors function as desired.
Second order effects: In the scaling process some second order device
characteristics, such as subthreshold operation, are usually ignored or
paid less attention, and their cancellation is more desired than their
improvement.
Mismatch: Mismatch in CMOS devices is relatively high. This is
specially hindering the reliability of analog processing in vision chips.
CMOS NOR GATE
If any input is high, the output is pulled low
If all inputs are low, the output is pulled high
CMOS FABRICATION
CMOS transistors are fabricated on silicon
wafer
Lithography process similar to printing press
On each step, different materials are
deposited or etched
Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process
INVERTER CROSS-SECTION
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
WELL AND SUBSTRATE TAPS
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
well
substrate tap
tap
INVERTER MASK SET
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
DETAILED MASK VIEWS
Six masks
n-well n well
Polysilicon
n+ diffusion
p+ diffusion
Polysilicon
Contact
Metal n+ Diffusion
p+ Diffusion
Contact
Metal
FABRICATION
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
FABRICATION STEPS
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
OXIDATION
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
PHOTORESIST
Spin on photoresist
Photoresistis a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
LITHOGRAPHY
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
ETCH
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been
exposed
Photoresist
SiO2
p substrate
STRIP PHOTORESIST
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
SiO2
p substrate
N-WELL
n-well is formed with diffusion or ion
implantation
Diffusion
Placewafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
STRIP OXIDE
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
n well
p substrate
POLYSILICON
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
POLYSILICON PATTERNING
Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
SELF-ALIGNED PROCESS
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-
well contact
n well
p substrate
N-DIFFUSION
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn't melt during later processing
n+ Diffusion
n well
p substrate
N-DIFFUSION CONT.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+ n+ n+
n well
p substrate
Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
P-DIFFUSION
Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
CONTACTS
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
METALIZATION
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
LAYOUT
Chips are specified with set of masks
Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
Feature size f = distance between source and
drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing
design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
SIMPLIFIED DESIGN RULES
Conservative rules to get you started
