DIFFERENTIAL

AMPLIFIER
 Why Differential Amplifier?

• Consider an Integrated Circuit on which Clock Line is running very close to wire coming as input
from Antenna

• The capacitive coupling between this two lines can distort the very small signal of antenna at
rising and falling edges of Clock as shown

• How we can get rid of this noise?

 What is Differential Signaling?

Signal ended Signal Differential Signal

• Differential signaling is a method of signal transfer that uses two signal paths.

• Whereas the alternative, single-ended signaling, transmits signals between one signal path and
a reference ground path

• Differential signaling transmits signals between two signal paths and a reference ground path

• The both signals have equal magnitude and opposite polarity which can be created by passing it
through Inverting Stage or say 180 degree phase shifter
• What if we take Differential Signals from the Antenna?

• Noise will affect both signals in same way and hence we could term it as “Common Mode
Signal” i.e. common to both signals

• So by superposition we can separate the 2 signals as Sine wave + Noise

• Mathematically we can write pure sine wave as

• Similarly noise signal (common mode signal) can be represented as

𝑉 1 +𝑉 2
𝑉 𝐶𝑀 =
2
 Important Points to Note
• The Voltages Vd and Vcm are just mathematically calculated signals

• This mathematical representation helps us to visualise the fact that total signal which
we call input is addition of Original Signal and Noise

• In rest if the slides if we are applying differential signal it does not mean that we are
applying Vd

• We always apply V1 and V2 as inputs to the circuit

Common Mode Rejection Ratio
• We want to have circuit which Amplifies Differential signal and
Attenuates Common Mode signal

• Gain for Common Mode Signal should be as LOW as possible and

Differential Gain should be HIGH

• Let us define one term called as Common Mode Rejection Ratio

i.e. CMRR

• Ideally our circuit should have INFINITE CMRR i.e. Gain for
common mode signal is ZERO

• Let us think of the Circuit which can have such characteristics

 Important Terminologies

• Differential Signal : Inputs which are 180 degree out of phase i.e. if one signal is increasing other signal is
decreasing and vice a versa

• Common Mode Signal : If certain signal is common to both the inputs i.e. both of them increase or
decrease simultaneously

• Observations:

1. Noise is common mode signal as it attacks the Differential Signals in similar manner

2. DC bias for transistor is applied to ensure Saturation region of operation, and it is same for both
transistors. Hence DC bias can also be considered as Common Mode Signal
 Common Source Amplifier

• If we consider our normal Common Source Amplifier, it will amplify the Signal and also Noise

• As common source stage is inverting stage, we get 180° phase shift between input and output for
both signal and noise

• As due to Sudden rise in Gate Voltage, Gate Source voltage increases which increases Drain
current and hence decrease in output voltage

• This circuit is amplifying noise with same gain as an signal

Will this circuit work as Differential Amplifier?

• If we apply noise affected differential signal to this circuit it will also amplify the noise signal

• The subtraction of 2 signals can give as Noise-Free signal, but this will again need one circuitry which
can subtract two signals available at output, hence this circuit does not have inbuilt property of giving
Noise free Output. So this does NOT work as Differential Amplifier.

• Main purpose of our design is that, it should amplify signal in BLACK and attenuate the signal in RED

• In both inputs we can see, black part is differential i.e. if one is increasing second one is decreasing
and RED signal is increasing/ decreasing in both input signals simultaneously

• Let us understand why this circuit is not attenuating the RED signal
• If we assume the MOSFET is working in Saturation for given DC voltages
• For this DC value of Gate as 1V , due to the drain current let us assume Vout1 and Vout2 both
are 4V (no AC applied)
• If we change that DC bias of both transistors to 2V (No AC applied), it will increase effective
Gate-Source Voltage
• This leads increase in the Drain Current which increases drop across Resistance and effectively
decreases the Vout1 and Vout2 both (say to 3V). So operation of the circuit depends on DC bias
level.
• Similarly, if we apply differential signal (AC) with noise (common to both inputs just like DC bias )
on top of DC bias, that will amplify the signal as well as noise because both signal and noise
changes the input and therefore Drain Current is changed resulting in a change in Vout1 and
Vout1.
• This circuit is Common Mode signal dependent as well as DC bias dependent
 Why the Circuit is Amplifying
Common Mode Signal?
• Important point to note in this circuit is that, for this circuit Source Voltage is fixed to ground

• Hence for any change in Gate Voltage (either differential or common mode) effective Gate-
Source voltage is changed

• As the result we get change in Drain current and as a result output voltage is changed

• For Common Mode signals, if Drain Current does not change, it will not change the output
voltage for same

• How this thing can be done?

• What if we add an constant current source at the bottom of transistors?

 Long Tail Differential Amplifier

• As tail current is 2mA, for DC voltage of 2V at Gate, Node Z voltage is set such that 1mA will flow through
both transistors M1 and M2

• As the both transistors have same Gate-Source voltage, they will carry same current and to satisfy KCL both
transistors will have current of 1mA through them which generate Vout say as 3V

• If the input voltage for both transistors is increased to 3V, still Gate-Source voltage is same and current
source at bottom will not change its value

• Hence Voltage at node Z is increased to maintain current 1mA from both and output is unchanged as 3V so
we can say this circuit is insensitive to DC bias voltages and Common Mode signals
 Common Mode Operation : In general

• If they share Constant Current source at Tail, then for common signals, current in both branches is set to I/2

• Still if Common Signal increases or Decreases, current through transistors will remain SAME by adjusting
the voltage at Node X

• Hence output voltage will remain same/unchanged for any common mode signals

• This is how attenuation is achieved for common mode signals

 Differential Mode Operation

• Say, for the applied DC bias of 2V at both inputs, both M1 and M2 have 1mA current in each branch i.e. total tail
current of 2mA (no AC is applied)

• If we apply 1V peak to peak differential sine wave over DC bias, assume we are at positive peak for Vin1, hence
Vin2 will at negative peak

• As Gate to Source voltage is more for M1 (than M2), it will conduct more current say 1.5mA than M2 say 0.5mA
maintaining 2mA total current which changes is Vout1 and Vout2

• Voltage by which Gate voltage goes UP for M1 transistor, same goes DOWN for M2 and hence with respect to
differential signal Node Z voltage is unchanged i.e. AC Ground
 Differential Mode Operation : In general

• For differential signal, if one input voltage increases the second input decrease (AC voltage)
• Hence the current is shared more towards voltage increased side and drops other side, satisfying KCL

• Voltage at Node X does not change in this condition as both inputs are Increasing and Decreasing by
same amount of voltage so KVL is satisfied
• Increase in Vin1 cause, increase of current in left branch, which increases the drop across R1 causing
Vout1 to decrease and similarly decrease for Vin2, Vout2 is increased
• Hence we get amplification for the differential signal as output is being modulated due to it
 Qualitative Analysis

• Let us assume, Vin1 – Vin2 varies from - If Vin1 is much negative than Vin2, M1 is OFF thus Vout1 = VDD and
all current Iss flows through M2 producing Vout2 as

• As Vin1 starts moving closer to Vin2, M1 starts sharing current and hence Vout1 starts falling. As a result M2
starts conducting with less current as , causing Vout2 to rise

• When both Vin1 and Vin2 are equal, both transistors will conduct with current () and Vout1, Vout2 is equal to

• If Vin1 increases than Vin2, M1 will start conducting all current which will turn OFF M2 and Vout2 = VDD and
Vout1 as
 Qualitative Analysis – contd.

• Our objective is to determine Vout1 − Vout2 as a function of Vin1 − Vin2

• We have
Vout1 = VDD − RD1 ID1 and Vout2 = VDD − RD2 ID2,
that is,
Vout1 − Vout2 = RD2 ID2 − RD1 ID1
= RD(ID2 − ID1); if RD1 = RD2 = RD

• Thus, we simply calculate ID1 and ID2 in terms of Vin1 and Vin2, assuming the circuit is symmetric, M1 and
M2 are saturated
• Since the voltage at node P is equal to VP = VS1 = VS2
• As we know, VGS1 = VG1 - VS1 = Vin1 - VP So, VP = Vin1 − VGS1 and
similarly, VP = Vin2 − VGS2 . So, by equating them we get,

• As per the I-V relationship of MOSFET we can say

• Hence rearranging it we get

• Substituting in 1st equation we get

• Assumption : Both transistors have same threshold voltage

• We wish to calculate the differential output current, ID1 − ID2.
Squaring the two sides of equation and recognizing that I D1 +
ID2 = ISS, we obtain

• That is

• Squaring the two sides again and 4ID1 ID2 = (ID1+ID2)2− (ID1−ID2)2
= I2SS − (ID1−ID2)2, we arrive at
Currents as function of Input Voltage
• Vin1 – Vin2 is referred as ∆Vin in this Figure

• Let us assume, Vin1 – Vin2 varies from - If Vin1 is much

negative than Vin2, M1 is OFF

• Hence ID1 is ZERO and ID2 will be Iss for maintaining KCL

• As we start increasing Vin1, then ID1 will start increasing

which makes ID2 to decrease to maintaining total current of
Iss

• If we further keep on increasing Vin1, M1 will be fully ON

having ID1 as Iss making M2 OFF with ID2 as Zero

• Bottom figure plots the ID1-ID2 as function of ∆Vin

• Slope of this plot is ∆I/∆Vin, which is nothing but

Transconductance (gm), which should be HIGH for having
High Gain
 Variation w.r.t. W/L and Iss

• If we keep Iss constant, and increase the W/L ratios of both transistor by same amount what will
happen?

• As Current is proportional to W/L, for that same Gate to Source Voltage we will get Higher
current for more W/L

• And as we are keeping Iss as constant, the maximum current limit is fixed, hence ∆Vin we can
give is now reduced (for small change in voltage now the current increases more (w.r.t low W/L
case)

• Hence slope increases, which means ∆I/∆Vin will be higher i.e. we are getting HIGHER
Transconductance
• If we keep W/L constant, and we increase Iss, then what will happen?

• Increasing tail current value will increase the maximum limit of current flowing through transistors

• So basically, we are increasing limits of ∆I i.e. ID1 – ID2

• So this will increase the input voltage limit (voltage swing) also but that would increase as a function
of ROOT of current

• Hence ∆I tends to more than ∆Vin and hence Transconductance increases i.e. Slope of Graph
increases (more steeper compared to left one)
Small Signal Gain : Differential Mode

• In the differential operation, Input at one side goes up by ∆V,

other side input goes down by same magnitude

• Hence, for such inputs the Source (DC) Voltage at node ‘P’
does not changes same as example in above shown circuit

• That node is considered as AC ground or Virtual Ground for

AC signals

• Hence it’s AC equivalent circuit can be represented as shown

in the figure on the left
• Lets take this example for better understanding of AC ground concept

• Calculate V using Superposition Theorem

• If we consider only 5V source : by voltage divider rule V1 = 2.5V

• And for -5V source : V2 = -2.5V

• So net voltage on the node V = V1 + V2 = 2.5V + (-2.5V) = 0V

• Similarly if we have inputs as 10V and -10V : Node voltage V remains at 0V (check the calculations by own)

• Analogy : Center Point of a Seesaw as constant point with same change on both sides in opposite direction
• From basic of single stage Common-Source Amplifier without Source degeneration we know that Gain
is –gmRD
 Key Features/Advatanges of Differential
Amplifier
• Circuits which amplify the Differential input signals and rejects common mode signal
have great advantages over single stage amplifier as:
1. Noise picked up by both inputs gets canceled in the output (common mode signal insensitivity)
2. If both inputs have same DC bias, the output is insensitive to changes in the bias

3. Input and feedback paths are isolated (this will be explained in next lecture, two stage OPAMP
design)

• CMRR is common mode rejection ratio, as it should be HIGH as possible (Ideally

Infinite) which is usually defined in dB

𝐶𝑀𝑅𝑅=
𝐴𝐷𝑖𝑓𝑓
𝐴 𝐶𝑀
=20 𝑙𝑜𝑔10
𝐴 𝐷𝑖𝑓𝑓
𝐴𝐶𝑀
𝑑𝐵( )
 Mathematical Definitions
• It is convenient to represent two input voltages and two output voltages as common
mode and differential signals

(input differential signal)

(input common mode signal)

(output differential signal)

(output common mode signal)

• Common Mode and Differential Gains are

 References for More Understanding
1. Design of Analog CMOS Integrated Circuits : B.Razavi

2. Youtube Lectures ‘Analog Integrated Circuit Design’ by Prof. Ali Hajimiri (Caltech University)

3. Youtube Lectures ‘Analog for Signal Processing - I’ by Prof. K. Radhakrishnan (IIT Madras)

4. Youtube Lectures ‘Analog VLSI Design’ by Indrajit Singh Dhanjal