Register Transfer and Micro-operations
Digital system design invariably uses a modular approach. The modules are constructed from digital components such as Registers, Decoders, arithmetic elements and control logic gates. The various modules are interconnected with common data and control paths.
So digital modules are best defined by the registers they contain and the operations that are performed on the data stored in them. The operations executed on the data stored in the registers are called Micro-operations. Examples of Micro-operations are Shift, Clear, Load etc.
Reg ister Transfer:
Comp u ter reg isters are d esig nated b y cap ital letters to d en o te the fun ctio n of th e register. Fo r ex amp le, th e reg ister that h o ld s the ad d ress fo r memo ry is d esig nated by th e n ame MAR o r AR.
In formation tran sfer fro m o ne reg ister to ano th er is d esig nated in sy mbo lic form
b y a rep lacemen t o p erato r. So R 2 R1 d en o tes a tran sfer of th e co n ten t o f R 1 to R2.
No rmally we wan t th e tran sfer to o ccur o nly u n d er pred etermin ed co n trol co n ditio n.
This can b e sh own b y mean s o f an If a nd then statemen t .
Wh ere P is a con trol sign al g en erated in th e co ntro l circu it. Th e co n tro l fu nctio n is in clu d ed in the statemen t as
n
Ev ery statemen t written in a register tran sfer n o tatio n req uires a h ardware co n stru ctio n for
imp lemen tin g th e tran sfer. Fig . b elo w sh o ws the d iag ram th at d ep icts th e tran sfer.
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Memory Transfer:
The transfer of information from Memory to the outside is called Read operation.
The transfer of new information to be stored into Memory is called a Write operation. A Memory word is sym bolized by the letter M. It is necessary to specify the address of M which will be done by enclosing the address in square bracket following the letter M.
Consider a transfer of information from Memory word M selected by the address in AR register into DR register. Its symbolic representation is Read : DR M [AR ].
The write operation transfers the content of DR register to a particular address of Memory. Its symbolic representation is Write : M [AR ] R1.
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BUS SYSTEM
A typical digital computer has many registers and paths must be provided to transfer
information from one register to another one. An efficient scheme for transferring information between registers is a common Bus System.
A Bus structure consists of a set of common lines , one for each digit of a register through which binary information is transferred one at a time. Control signals determine which register is selected by the Bus during each particular register transfer.
One way of constructing a common Bus system is with Multiplexers which selects the source register whose binary information is then placed on the Bus.
The construction of a Bus System for four registers each of size four bit is shown below:-
BUS SYSTEM
In general a Bus System will multiplex k- registers of size n bits each to produce an n line common bus.
No. of Multiplexers required is n and size of each Multiplexer k x 1 .
The no. of selection lines needed for each Multiplexer is s such that 2s =k
The transfer of information from a Bus into one of the destination registers can be accomplished by connecting the Bus lines to the inputs of all registers and activating
the Load control of a particular one. So the transfer
is implemented by the transfer .
From this statement the designer knows which control signal must be activated to
produce a transfer through the Bus.
THREE STATE BUS BUFFER
A Bus System can be constructed with Three State Buffer Gates instead of Multiplexers. A Three State Gate is a digital circuit that exhibits three states.
Two of the states are signals equivalent to logic 1 and 0 as in conventional
gates. The third state is a high impedance state which behaves like an open
circuit.
The control input determines the output state. When the control input is equal
to 1, the output is enabled but when the control input is equal to 0 , the output is disabled and the gate goes to a high impedance state.
The construction of a Bus System with Three State Buffers is shown below:-
The control inputs of the Buffer will determine which one of the four normal inputs
will communicate with the Bus line. No more than one Buffer will be active at any time. One way to ensure that is to use a Decoder. When the Enable input of the Decoder is 0, all its outputs are 0 and the Bus line is in high impedance state. When
Enable input is active, depending on the binary value of the select inputs of the Decoder , one of the Buffers will be active.
To construct a common Bus for four registers of n bit each, we need n such circuits
having common select inputs.
