STM32F407 Microcontroller

Overview
Archana D

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Agenda

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Overview of STM32F4 Series
 Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168
MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
 Memories
– Up to 1 Mbyte of flash memory
– Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory)
data RAM – 512 bytes of OTP memory – Flexible static memory controller supporting
Compact Flash, SRAM, PSRAM, NOR and NAND memories
 LCD parallel interface, 8080/6800 modes
 Clock, reset, and supply management
– 1.8 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration

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  Low-power operation
– Sleep, Stop, and Standby modes
– VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM

 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple
interleaved mode
 2×12-bit D/A converters
 General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
 Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each
with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder
input
 Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
 Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 84 MHz
– Up to 138 5 V-tolerant I/Os

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  Up to 15 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
– Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy
via internal audio PLL or external clock
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
 Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip
full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
 8- to 14-bit parallel camera interface up to 54 Mbytes/s
 True random number generator
 CRC calculation unit
 96-bit unique ID
 RTC: subsecond accuracy, hardware calendar

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Device summary

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STM32F405xx and STM32F407xx: features and
peripheral counts

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Common STM32F407 Variants
Flash SRAM Package Key Varian Flash Package
Variant GPIOs SRAM Size
Size Size Type Features t Size Type
USB OTG
FS/HS, STM32
STM32F407VGT6 1 MB 192 KB LQFP100 82 Ethernet, F407V 1 MB 192 KB LQFP100
Camera, GT6
CAN, SDIO
Same as STM32
STM32F407ZGT6 1 MB 192 KB LQFP144 114 above, F407Z 1 MB 192 KB LQFP144
more GPIOs GT6
Max GPIOs,
LQFP176 / STM32
rich LQFP176 /
STM32F407IGT6 1 MB 192 KB UFBGA17 140 F407IG 1 MB 192 KB
peripheral UFBGA176
6 T6
set
Same
STM32
peripheral
STM32F407VET6 512 KB 192 KB LQFP100 82 F407VE 512 KB 192 KB LQFP100
set, smaller
T6
flash
STM32
STM32F407ZET6 512 KB 192 KB LQFP144 114 F407ZE 512 KB 192 KB LQFP144
T6
LQFP176 / STM32
LQFP176 /
STM32F407IET6 512 KB 192 KB UFBGA17 140 F407IE 512 KB 192 KB
UFBGA176
6 T6
Industrial
STM32
temperatur
STM32F407VGT7 1 MB 192 KB LQFP100 82 F407V 1 MB 192 KB LQFP100
e range
GT7
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STM32 Product Lines

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STM32 Value Line Block Diagram

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Arm® Cortex®-M4 core with FPU and embedded
Flash and SRAM
 The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors
for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and low-power
consumption, while delivering outstanding computational performance and an
advanced response to interrupts.
 The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the
memory size usually associated with 8- and 16-bit devices.
 The processor supports a set of DSP instructions which allow efficient signal
processing and complex algorithm execution.
 Its single precision FPU (floating point unit) speeds up software development by
using metalanguage development tools, while avoiding saturation.
 The STM32F405xx and STM32F407xx family is compatible with all Arm tools and
software.

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Adaptive real-time memory accelerator
(ART Accelerator)
 The ART Accelerator is a memory accelerator which is optimized for STM32
industry-standard Arm® Cortex®-M4 with FPU processors.
 It balances the inherent performance advantage of the Arm Cortex-M4 with FPU
over flash memory technologies, which normally requires the processor to wait for
the flash memory at higher frequencies.
 To release the processor full 210 DMIPS performance at this frequency, the
accelerator implements an instruction prefetch queue and branch cache, which
increases program execution speed from the 128-bit flash memory.
 Based on CoreMark benchmark, the performance achieved thanks to the ART
accelerator is equivalent to 0 wait state program execution from flash memory at
a CPU frequency up to 168 MHz.

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Memory protection unit

 The memory protection unit (MPU) is used to manage the CPU accesses to
memory to prevent one task to accidentally corrupt the memory or resources used
by any other active task. This memory area is organized into up to 8 protected
areas that can in turn be divided up into 8 subareas.
 The protection area sizes are between 32 bytes and the whole 4 gigabytes of
addressable memory.
 The MPU is especially helpful for applications where some critical or certified code
has to be protected against the misbehavior of other tasks. It is usually managed
by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action.
 In an RTOS environment, the kernel can dynamically update the MPU area setting,
based on the process to be executed.

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Embedded flash memory

 The STM32F40xxx devices embed a flash memory of 512 Kbytes or 1 Mbytes

available for storing programs and data, plus 512 bytes of OTP memory.

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CRC (cyclic redundancy check) calculation
unit
 The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from
a 32-bit data word and a fixed generator polynomial.
 Among other applications, CRC-based techniques are used to verify data
transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard,
they offer a means of verifying the flash memory integrity.
 The CRC calculation unit helps compute a software signature during runtime, to be
compared with a reference signature generated at link-time and stored at a given
memory location.

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CRC calculation unit block diagram

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  The CRC calculation unit mainly consists of a single 32-bit data register, which is
used as an input register to enter new data in the CRC calculator (when writing
into the register) holds the result of the previous CRC calculation (when reading
the register)
 Each write operation into the data register creates a combination of the previous
CRC value and the new one (CRC computation is done on the whole 32-bit data
word, and not byte per byte).
 The write operation is stalled until the end of the CRC computation, thus allowing
back-toback write accesses or consecutive write and read accesses.
 The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR
register

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Embedded SRAM

 All STM32F40xxx products embed:

 • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled
memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with
0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the
CPU. Its content is protected against possible unwanted write accesses, and is
retained in Standby or VBAT mode.

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DMA controller (DMA)

 The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. They feature dedicated FIFOs for
APB/AHB peripherals, support burst transfer and are designed to provide the
maximum peripheral bandwidth (AHB/APB).
 The two DMA controllers support circular buffer management, so that no specific
code is needed when the controller reaches the end of the buffer. The two DMA
controllers also have a double buffering feature, which automates the use and
switching of two memory buffers without requiring any special code.
 Each stream is connected to dedicated hardware DMA requests, with support for
software trigger on each stream. Configuration is made by software and transfer
sizes between source and destination are independent.
 The DMA can be used with the main peripherals:
 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers
TIMx • DAC • SDIO • Camera interface (DCMI) • ADC.

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Flexible static memory controller (FSMC)

 The FSMC is embedded in the STM32F405xx and STM32F407xx family.

 It has four Chip Select outputs supporting the following modes: PCCard/Compact
Flash, SRAM, PSRAM, NOR Flash and NAND Flash.
Functionality overview:
Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.

LCD parallel interface

 The FSMC can be configured to interface seamlessly with most graphic LCD
controllers.
 It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to
adapt to specific LCD interfaces.
 This LCD parallel interface capability makes it easy to build cost-effective graphic
applications using LCD modules with embedded controllers or high performance
solutions using external controllers with dedicated acceleration

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Nested vectored interrupt controller
(NVIC)
 The STM32F405xx and STM32F407xx embed a nested vectored interrupt
controller able to manage 16 priority levels, and handle up to 82 maskable
interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU core.
 Closely coupled NVIC gives low-latency interrupt processing
 Interrupt entry vector table address passed directly to the core
 Allows early processing of interrupts
 Processing of late arriving, higher-priority interrupts
 Support tail chaining • Processor state automatically saved
 Interrupt entry restored on interrupt exit with no instruction overhead

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External interrupt/event controller (EXTI)

 The external interrupt/event controller consists of 23 edge-detector lines used to

generate interrupt/event requests.
 Each line can be independently configured to select the trigger event (rising edge,
falling edge, both) and can be masked independently.
 A pending register maintains the status of the interrupt requests. The EXTI can
detect an external line with a pulse width shorter than the Internal APB2 clock
period. Up to 140 GPIOs can be connected to the 16 external interrupt lines

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Clocks and startup

 On reset the 16 MHz internal RC oscillator is selected as the default CPU clock.
The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the
full temperature range.
 The application can then select as system clock either the RC oscillator or an
external 4-26 MHz clock source. This clock can be monitored for failure.
 If a failure is detected, the system automatically switches back to the internal RC
oscillator and a software interrupt is generated (if enabled).
 This clock source is input to a PLL thus allowing to increase the frequency up to
168 MHz. Similarly, full interrupt management of the PLL clock entry is available
when necessary

 Several prescalers allow the configuration of the three AHB buses, the high-speed
APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of
the three AHB buses is 168 MHz while the maximum frequency of the high-speed
APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB
domain is 42 MHz.

 The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard
sampling
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Boot modes

 At startup, boot pins are used to select one out of three boot options:
 • Boot from user Flash • Boot from system memory • Boot from embedded SRAM
 The boot loader is located in system memory. It is used to reprogram the flash
memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2
(PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device
firmware upgrade).

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Power Controller
Power supplies
 The device requires a 1.8 to 3.6 V operating voltage supply (VDD). An embedded
linear
 voltage regulator is used to supply the internal 1.2 V digital power.
 The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP
SRAM)
 can be powered from the VBAT voltage when the main VDD supply is powered off.

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Power supplies

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Power supply supervisor
 Internal reset ON

 On packages embedding the PDR_ON pin, the power supply supervisor is enabled
by holding PDR_ON high. On all other packages, the power supply supervisor is
always enabled.
 The device has an integrated power-on reset (POR) / power-down reset (PDR)
circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is
always active and ensures proper operation starting from 1.8 V. After the 1.8 V
POR threshold level is reached, the option byte loading process starts, either to
confirm or modify default BOR threshold levels, or to disable BOR permanently.
Three BOR thresholds are available through option bytes. The device remains in
reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without
the need for an external reset circuit.

 The device also features an embedded programmable voltage detector (PVD) that
monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold
and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service
routine can then generate a warning message and/or put the MCU into a safe
state. The PVD is enabled by software.
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  Internal reset OFF

 This feature is available only on packages featuring the PDR_ON pin. The internal
power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the
PDR_ON pin.
 An external power supply supervisor should monitor VDD and should maintain the
device in reset mode as long as VDD is below a specified threshold. PDR_ON
should be connected to this external power supply supervisor.

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  A comprehensive set of power-saving mode allows to design low-power
applications.
 When the internal reset is OFF, the following integrated features are no more
supported:
 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is
disabled • The brownout reset (BOR) circuitry is disabled • The embedded
programmable voltage detector (PVD) is disabled • VBAT functionality is no more
available and VBAT pin should be connected to VDD

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Voltage regulator

 The regulator has four operating modes:

• Regulator ON – Main regulator mode (MR) – Low-power regulator (LPR) – Power-
down
 Regulator OFF

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Regulator ON

 On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.
 There are three power modes configured by software when regulator is ON:
 MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach
the best compromise between maximum frequency and dynamic power
consumption.
 LPR is used in the Stop modes The LP regulator mode is configured by software
when entering Stop mode.
 Power-down is used in Standby mode.
 The Power-down mode is activated only when entering in Standby mode. The
regulator output is in high impedance and the kernel circuitry is powered down,
inducing zero consumption. The contents of the registers and SRAM are lost)

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Regulator OFF

 This feature is available only on packages featuring the BYPASS_REG pin. The
regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows
to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
 Since the internal voltage scaling is not manage internally, the external voltage
value must be aligned with the targeted maximum frequency. The two 2.2 μF
ceramic capacitors should be replaced by two 100 nF decoupling capacitors.
 When the regulator is OFF, there is no more internal monitoring on V12. An
external power supply supervisor should be used to monitor the V12 of the logic
power domain. PA0 pin should be used for this purpose, and act as power-on reset
on V12 power domain.

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Real-time clock (RTC), backup SRAM and
backup registers
 The backup domain of the STM32F405xx and STM32F407xx includes:
 The real-time clock (RTC)
 4 Kbytes of backup SRAM
 20 backup registers

 The real-time clock (RTC) is an independent BCD timer/counter. Dedicated

registers contain the second, minute, hour (in 12/24 hour), week day, date,
month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap
year), 30, and 31 day of the month are performed automatically. The RTC provides
a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary
format.

 It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal

low-power RC oscillator or the high-speed external clock divided by 2 to 31. The
internal low-speed RC has a typical frequency of 32 kHz. The RTC can be
calibrated using an external 512 Hz output to compensate for any natural quartz
deviation.

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  Two alarm registers are used to generate an alarm at a specific time and calendar
fields can be independently masked for alarm comparison. To generate a periodic
interrupt, a 16-bit programmable binary auto-reload downcounter with
programmable resolution is available and allows automatic wakeup and periodic
alarms from every 120 μs to every 36 hours.

 A 20-bit prescaler is used for the time base clock. It is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz.

 The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store
data which need to be retained in VBAT and standby mode. This memory area is
disabled by default to minimize power consumption It can be enabled by software.
 The backup registers are 32-bit registers used to store 80 bytes of user application
data when VDD power is not present. Backup registers are not reset by a system, a
power reset, or when the device wakes up from the Standby mode
 Additional 32-bit registers contain the programmable alarm subseconds, seconds,
minutes, hours, day, and date.
 Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.

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Low-power modes

 The STM32F405xx and STM32F407xx support three low-power modes to achieve

the best compromise between low-power consumption, short startup time and
available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
Stop mode The Stop mode achieves the lowest power consumption while retaining
the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL,
the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also
be put either in normal or in low-power mode. The device can be woken up from the
Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external
lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB
OTG FS/HS wakeup or the Ethernet wakeup).
Standby mode The Standby mode is used to achieve the lowest power consumption.
The internal voltage regulator is switched off so that the entire V12 domain is
powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off.
After entering Standby mode, the SRAM and register contents are lost except for
registers in the backup domain and the backup SRAM when selected. The device exits
the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on
the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The
standby
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Proprietary not supported when the embedded
40 voltage regulator is bypassed
VBAT operation

 The VBAT pin allows to power the device VBAT domain from an external battery,
an external supercapacitor, or from VDD when no external battery and an external
supercapacitor are present.
 VBAT operation is activated when VDD is not present.
 The VBAT pin supplies the RTC, the backup registers and the backup SRAM.

Note:When the microcontroller is supplied from VBAT, external interrupts and RTC
alarm/events do not exit it from VBAT operation.
When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality
is no more available and VBAT pin should be connected to VDD.

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Timers

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Independent watchdog

 The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler.

It is clocked from an independent 32 kHz internal RC and as it operates
independently from the main clock, it can operate in Stop and Standby modes.
 It can be used either as a watchdog to reset the device when a problem occurs, or
as a free-running timer for application timeout management.
 It is hardware- or software-configurable through the option bytes.

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Window watchdog

 The window watchdog is based on a 7-bit downcounter that can be set as free-
running.
 It can be used as a watchdog to reset the device when a problem occurs.
 It is clocked from the main clock. It has an early warning interrupt capability and
the counter can be frozen in debug mode.

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SysTick timer

 This timer is dedicated to real-time operating systems, but could also be used as a
standard downcounter. It features:
 A 24-bit downcounter
 Autoreload capability
 Maskable system interrupt generation when the counter reaches 0
 Programmable clock source.

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Inter-integrated circuit interface (I²C)

 Up to three I²C bus interfaces can operate in multimaster and slave modes. They
can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz).
They support the 7/10-bit addressing mode and the 7-bit dual addressing mode
(as slave). A hardware CRC generation/verification is embedded.
 They can be served by DMA and they support SMBus 2.0/PMBus.

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Universal synchronous/asynchronous receiver
transmitters (USART)
 The STM32F405xx and STM32F407xx embed four universal
synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and
USART6) and two universal asynchronous receiver transmitters (UART4 and
UART5).
 These six interfaces provide asynchronous communication, IrDA SIR ENDEC
support, multiprocessor communication mode, single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART1 and
USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The
other available interfaces communicate at up to 5.25 Mbit/s.
 USART1, USART2, USART3 and USART6 also provide hardware management of the
CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like
communication capability.
 All interfaces can be served by the DMA controller

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Serial peripheral interface (SPI)

 The STM32F40xxx feature up to three SPIs in slave and master modes in full-
duplex and simplex communication modes. SPI1 can communicate at up to 42
Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler
gives 8 master mode frequencies and the frame is configurable to 8 bits or 16
bits. The hardware CRC generation/verification supports basic SD Card/MMC
modes. All SPIs can be served by the DMA controller.
 The SPI interface can be configured to operate in TI mode for communications in
master mode and slave mode.

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Inter-integrated sound (I2S)

 Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available.
 They can be operated in master or slave mode, in full duplex and half-duplex
communication modes, and can be configured to operate with a 16-/32-bit
resolution as an input or output channel.
 Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either
or both of the I2S interfaces is/are configured in master mode, the master clock
can be output to the external DAC/CODEC at 256 times the sampling frequency.
 All I2Sx can be served by the DMA controller.

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Audio PLL (PLLI2S)

 The devices feature an additional dedicated PLL for audio I2S application. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the
CPU performance, while using USB peripherals.
 The PLLI2S configuration can be modified to manage an I2S sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
 The audio PLL can be programmed with very low error to obtain sampling rates
ranging from 8 KHz to 192 KHz.
 In addition to the audio PLL, a master clock input pin can be used to synchronize
the I2S flow with an external PLL (or Codec output).

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Secure digital input/output interface
(SDIO)
 Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit
and 8-bit.
 The interface allows data transfer at up to 48 MHz, and is compliant with the SD
Memory Card Specification Version 2.0.
 The SDIO Card Specification Version 2.0 is also supported with two different
databus modes: 1-bit and 4-bit.
 The current version supports only one SD/SDIO/MMC4.2 card at any one time and
a stack of MMC4.1 or previous.

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Ethernet MAC interface with dedicated DMA and
IEEE 1588 support
 Peripheral available only on the STM32F407xx devices.
 The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access
controller (MAC) for ethernet LAN communications through an industry-standard
medium-independent interface (MII) or a reduced medium-independent interface
(RMII).
 The STM32F407xx requires an external physical interface device (PHY) to connect
to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the
STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be
clocked using the 25 MHz (MII) from the STM32F407xx

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 The STM32F407xx includes the following features:
 Supports 10 and 100 Mbit/s rates
 Dedicated DMA controller allowing high-speed transfers between the dedicated
SRAM and the descriptors (see the STM32F40xxx/41xxx reference manual for
details)
 Tagged MAC frame support (VLAN support)
 Half-duplex (CSMA/CD) and full-duplex operation
 MAC control sublayer (control frames) support
 32-bit CRC generation and removal
 Several address filtering modes for physical and multicast address (multicast and
group addresses)
 32-bit status code for each transmitted or received frame
 Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
 Supports hardware PTP (precision time protocol) in accordance with IEEE 1588
2008 (PTP V2) with the time stamp comparator connected to the TIM2 input
 Triggers interrupt when system time becomes greater than target time

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Controller area network (bxCAN)

 The two CANs are compliant with the 2.0A and B (active) specifications with a
bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
 Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28
shared scalable filter banks (all of them can be used even if one CAN is used). 256
bytes of SRAM are allocated for each CAN.

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Universal serial bus on-the-go full-speed
(OTG_FS)
The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with
the USB 2.0 specification and with the OTG 1.0 specification. It has software-
configurable endpoint setting and supports suspend/resume. The USB OTG full-speed
controller requires a dedicated 48 MHz clock that is generated by a PLL connected to
the HSE oscillator.
The major features are:
 Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
 Supports the session request protocol (SRP) and host negotiation protocol
(HNP)
 4 bidirectional endpoints
 8 host channels with periodic OUT support
 HNP/SNP/IP inside (no need for any external resistor)
 For OTG/Host modes, a power switch is needed in case bus-powered devices
are connected

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Digital camera interface (DCMI)

 STM32F407xx products embed a camera interface that can connect with camera
modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive
video data.
 The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz.

It features:
 Programmable polarity for the input pixel clock and synchronization signals
 Parallel data communication can be 8-, 10-, 12- or 14-bit
 Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
 Supports continuous mode or snapshot (a single frame) mode
 Capability to automatically crop the image

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True random number generator (RNG)

 All STM32F405xx and STM32F407xx products embed a true random number

generator (RNG) that provides full entropy outputs to the application as 32-bit
samples.
 It is composed of a live entropy source (analog) and an internal conditioning
component.

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General-purpose input/outputs (GPIOs)

 Each of the GPIO pins can be configured by software as output (push-pull or open-
drain, with or without pull-up or pull-down), as input (floating, with or without pull-
up or pull-down) or as peripheral alternate function.
 Most of the GPIO pins are shared with digital or analog alternate functions. All
GPIOs are high-current-capable and have speed selection to better manage
internal noise, power consumption and electromagnetic emission.
 The I/O configuration can be locked if needed by following a specific sequence in
order to avoid spurious writing to the I/Os registers.
 Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

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Analog-to-digital converters (ADCs)

 Three 12-bit analog-to-digital converters are embedded and each ADC shares up
to 16 external channels, performing conversions in the single-shot or scan mode.
 In scan mode, automatic conversion is performed on a selected group of analog
inputs.
 Additional logic functions embedded in the ADC interface allow:

Simultaneous sample and hold

Interleaved sample and hold

 The ADC can be served by the DMA controller. An analog watchdog feature allows
very precise monitoring of the converted voltage of one, some or all selected
channels. An interrupt is generated when the converted voltage is outside the
programmed thresholds.

 To synchronize A/D conversion and timers, the ADCs could be triggered by any of
TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer

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Temperature sensor

 The temperature sensor has to generate a voltage that varies linearly with
temperature. The conversion range is between 1.8 V and 3.6 V. The temperature
sensor is internally connected to the ADC1_IN16 input channel which is used to
convert the sensor output voltage into a digital value.
 As the offset of the temperature sensor varies from chip to chip due to process
variation, the internal temperature sensor is mainly suitable for applications that
detect temperature changes instead of absolute temperatures. If an accurate
temperature reading is needed, then an external temperature sensor part should
be used.

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Digital-to-analog converter (DAC)

 The two 12-bit buffered DAC channels can be used to convert two digital signals
into two analog voltage signal outputs.

 This dual digital Interface supports the following features:

 two DAC converters: one for each output channel
 8-bit or 12-bit monotonic output
 left or right data alignment in 12-bit mode
 synchronized update capability • noise-wave generation
 triangular-wave generation
 dual DAC channel independent or simultaneous conversions
 DMA capability for each channel
 external triggers for conversion
 input voltage reference VREF+

 Eight DAC trigger inputs are used in the device. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA
streams

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Serial wire JTAG debug port (SWJ-DP)

 The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire
debug port that enables either a serial wire debug or a JTAG probe to be
connected to the target.
 Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins
could be re-use as GPIO with alternate function):
 the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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Embedded Trace Macrocell™

 The Arm Embedded Trace Macrocell provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high
rate from the STM32F40xxx through a small number of ETM pins to an external
hardware trace port analyser (TPA) device.
 The TPA is connected to a host computer using USB, Ethernet, or any other high-
speed channel. Real-time instruction and data flow activity can be recorded and
then formatted for display on the host computer that runs the debugger software.
TPA hardware is commercially available from common development tool vendors.
 The Embedded Trace Macrocell operates with third party debugger software tools.

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STM32F40xxx LQFP100 pinout

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Memory mapping

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Confidential and Proprietary C-2 67
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Confidential and Proprietary C-2 69
Confidential and Proprietary C-2 70
Memory and bus architecture
System architecture
 main system consists of 32-bit multilayer AHB bus matrix that interconnects:
 The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
 Eight masters
Cortex®-M4 with FPU core I-bus, D-bus and S-bus
DMA1 memory bus
DMA2 memory bus
DMA2 peripheral bus
Ethernet DMA bus
USB OTG HS DMA bus
 Seven slaves
Internal flash memory ICode bus
Internal flash memory DCode bus
Main internal SRAM1 (112 KB)
Auxiliary internal SRAM2 (16 KB)
AHB1 peripherals including AHB to APB bridges and APB peripherals
AHB2 peripherals – FSMC

Confidential and Proprietary C-2 71

System architecture for STM32F405xx/07xx

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 I-bus
 This bus connects the Instruction bus of the Cortex®-M4 with FPU core to the
BusMatrix.
 This bus is used by the core to fetch instructions.
 The target of this bus is a memory containing code (internal flash memory/SRAM
or external memories through the FSMC/FMC).

D-bus
 This bus connects the databus of the Cortex®-M4 with FPU to the 64-Kbyte CCM
data RAM to the BusMatrix. This bus is used by the core for literal load and debug
access.
 The target of this bus is a memory containing code or data (internal flash memory
or external memories through the FSMC/FMC)

S-bus
 This bus connects the system bus of the Cortex®-M4 with FPU core to a
BusMatrix.
 This bus is used to access data located in a peripheral or in SRAM.
 Instructions may also be fetched on this bus (less efficient than ICode).
 The targets of this bus are the internal SRAM1, SRAM2 and SRAM3, the AHB1
peripherals
Confidential and Proprietaryincluding
C-2 the APB peripherals,
73 the AHB2 peripherals and the external
 DMA memory bus
 This bus connects the DMA memory bus master interface to the BusMatrix.
 It is used by the DMA to perform transfer to/from memories.
 The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2 and
SRAM3) and external memories through the FSMC/FMC.

DMA peripheral bus

 This bus connects the DMA peripheral master bus interface to the BusMatrix.
 This bus is used by the DMA to access AHB peripherals or to perform memory-to-
memory transfers.
 The targets of this bus are the AHB and APB peripherals plus data memories:
internal SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the
FSMC/FMC

Ethernet DMA bus

 This bus connects the Ethernet DMA master interface to the BusMatrix.
 This bus is used by the Ethernet DMA to load/store data to a memory.
 The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2,
SRAM3), internal flash memory, and external memories through the FSMC/FMC

Confidential and Proprietary C-2 74

 USB OTG HS DMA bus
 This bus connects the USB OTG HS DMA master interface to the BusMatrix.
 This bus is used by the USB OTG DMA to load/store data to a memory.
 The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2,
SRAM3), internal flash memory, and external memories through the FSMC/FMC.

LCD-TFT controller DMA bus

 This bus connects the LCD controller DMA master interface to the BusMatrix.
 It is used by the LCD-TFT DMA to load/store data to a memory.
 The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2,
SRAM3), external memories through FMC, and internal flash memory.

DMA2D bus
This bus connect the DMA2D master interface to the BusMatrix.
This bus is used by the DMA2D graphic Accelerator to load/store data to a memory.
The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3),
external memories through FMC, and internal flash memory

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  BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses
a round-robin algorithm.

AHB/APB bridges (APB)

 The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections
between
 the AHB and the two APB buses, allowing flexible selection of the peripheral
frequency.
 After each device reset, all peripheral clocks are disabled (except for the SRAM
and flash
 memory interface).
 Before using a peripheral you have to enable its clock in the RCC_AHBxENR or
RCC_APBxENR register.

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Memory organization
 Program memory, data memory, registers and I/O ports are organized within the
same linear 4 Gbyte address space.
 The bytes are coded in memory in little-endian format. The lowest numbered byte
in a word is considered the word’s least significant byte and the highest numbered
byte, the word’s most significant.
 The addressable memory space is divided into 8 main blocks, each of 512 MB.

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Embedded SRAM

SRAM Block Address Range Access Notes

SRAM1 0x2000_0000 All AHB Masters Main system RAM

Part of the 192 KB

SRAM2 Follows SRAM1 All AHB Masters
total

Core Coupled
CPU Only (via D- Memory, not
CCM RAM 0x1000_0000
Bus) accessible by
DMA/peripherals

0x4002_4000 CPU (when VBAT is Retains data in

Backup SRAM
(typical) supplied) Standby mode

Confidential and Proprietary C-2 78

Boot configuration
 Due to its fixed memory map, the code area starts from address 0x0000 0000
(accessedthrough the ICode/DCode buses) while the data area (SRAM) starts from
address 0x2000 0000 (accessed through the system bus).
 The Cortex®-M4 with FPU CPU always fetches the reset vector on the ICode bus,
which implies to have the boot space available only in the code area (typically,
flash memory).
 STM32F4xx microcontrollers implement a special mechanism to be able to boot
from other memories (like the internal SRAM).

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Embedded flash memory interface
Introduction
 The flash memory interface manages CPU AHB I-Code and D-Code accesses to the
flash memory.
 It implements the erase and program flash memory operations and the read and
write protection mechanisms.
 The flash memory interface accelerates code execution with a system of
instruction prefetch
and cache lines.

Main features
 Flash memory read operations
 Flash memory program/erase operations
 Read / write protections
 Prefetch on I-Code
 64 cache lines of 128 bits on I-Code
 8 cache lines of 128 bits on D-Code

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Embedded flash memory in STM32F405xx/07xx
 The flash memory has the following main features:
 Capacity up to 1 Mbyte
 128 bits wide data read
 Byte, half-word, word and double word write
 Sector and mass erase
 Memory organization
 The flash memory is organized as follows:
 – A main memory block divided into 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes,
 and 7 sectors of 128 Kbytes
 – System memory from which the device boots in System memory boot mode
 – 512 OTP (one-time programmable) bytes for user data
 The OTP area contains 16 additional bytes used to lock the corresponding OTP
 data block.
 – Option bytes to configure read and write protection, BOR level, watchdog
 software/hardware and reset when the device is in Standby or Stop mode.
 Low-power modes (for details refer to the Power control (PWR) section of the
reference
 manual)

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Flash memory interface connection inside
system architecture

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Confidential and Proprietary C-2 83
Adaptive real-time memory accelerator
(ART

Accelerator)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for
STM32
 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the
inherent
 performance advantage of the Arm® Cortex®-M4 with FPU over flash memory
technologies,
 which normally requires the processor to wait for the flash memory at higher
operating
 frequencies.
 To release the processor full performance, the accelerator implements an
instruction
 prefetch queue and branch cache which increases program execution speed from
the 128-
 bit flash memory. Based on CoreMark benchmark, the performance achieved
thanks to the
 ART accelerator is equivalent to 0 wait state program execution from flash
memory at a
 CPU frequency up to 180 MHz.

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CRC calculation unit
CRC introduction
 The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from
a 32-bit data word and a fixed generator polynomial.
 Among other applications, CRC-based techniques are used to verify data
transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard,
they offer a means of verifying the flash memory integrity.
 The CRC calculation unit helps compute a signature of the software during
runtime, to be compared with a reference signature generated at link-time and
stored at a given memory location.

CRC main features

 Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
 – X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+
X+1
 • Single input/output 32-bit data register
 • CRC computation done in 4 AHB clock cycles (HCLK)
 • General-purpose 8-bit register (can be used for temporary storage)

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 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
• The ADC voltage supply input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on VSSA pin.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF. The voltage on VREF ranges from 1.8 V to VDDA.

Battery backup domain

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a
battery or by another source.
To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT
pin powers the following blocks:
• The RTC
• The LSE oscillator
• The backup SRAM when the low-power backup regulator is enabled
• PC13 to PC15 I/Os, plus PI8 I/O (when available)
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset
block.

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Reset and clock control for STM32F42xxx and
STM32F43xxx (RCC)
Reset
There are three types of reset, defined as system Reset, power Reset and backup
domain Reset.

System reset
 A system reset sets all registers to their reset values unless specified otherwise in
the register description
 A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)

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  Software reset
The reset source can be identified by checking the reset flags in the RCC clock control
&
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control
Register must be set to force a software reset on the device. Refer to the Cortex®-M4
with
FPU technical reference manual for more details.
 Low-power management reset
There are two ways of generating a low-power management reset:
1. Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2. Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.

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  Power reset
 A power reset is generated when one of the following events occurs:
 1. Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
 2. When exiting the Standby mode

Confidential and Proprietary C-2 89

 Thank
You
gtd_team@arigs.
com

www.arigs.co
m

Confidential and Proprietary C-2