ARCHITECTURE
OF
TMS320C3X
INTRODUCTION
• The TMS320C3X Series of digital signal processors are high performance
CMOS 32-bit floating point devices in the TMS320 family of single-chip
DSPs.
• The C3X devices integrates both system control and math intensive
functions on a single controller. This system integration allows fast, easy
data movement and high-speed numeric processing performance.
• Instruction set provides 60 million floating point operation per second
(MFLOPS) and 30 million fixed point instructions per second (MIPS).
Overview of TMS320C3X Devices
• C3X family consist of 3 members ‘C30’, ‘C31’, ‘C32’ .
• It can perform Parallel multiply and ALU Operations on integer or floating-point data in a
single cycle.
• Processors consists of:
1. General purpose register file
2. Program Cache
3. Dedicated auxiliary register arithmetic units (ARAU)
4. Internal dual-access memories
5. Large address space
Contd….
6. Direct memory access channel (DMA) supporting concurrent I/O
7. Multiprocessor interface
8. Internal and externally generated wait states
9. External interface ports
10. Timers
11. Serial ports and multiple-interrupt structure.
Central Processing Unit (CPU)
• The CPU is the core of the TMS320C3X and is designed to execute complex
operations efficiently and quickly.
1. Arithmetic Units Integer and Floating-Point Multiplier:
Supports 32-bit integer and IEEE 754 single-precision (32-bit) floating-
point multiplication.
Critical for DSP operations like convolution and matrix multiplication.
Can produce results in a single cycle due to its optimized architecture.
CPU Contd….
2. Integer and Floating-Point ALUe (Extended ALU):
Performs arithmetic and logical operations (ADD, SUB, AND, OR,
XOR, etc.)
ALUe is extended to support high-precision floating-point and integer
computations.
Handles type conversions (e.g., integer to float) and comparisons.
CPU Contd….
2. Registers
8 Extended-Precision Registers:
Used to hold operands and results of arithmetic operations.
Each is 32-bit wide, but can be paired for 64-bit operations.
3. Auxiliary Register Arithmetic unit:
The ARAU Operates in parallel with the multiplier, ALU and they are used for
indirect addressing mode.
They also support circular and bit-reversed addressing mode
CPU Contd…..
3. Address Generation Units (AGUs) Address Generation 0 & 1:
Allow two memory accesses per cycle (load/store) in parallel with computation.
Provide indirect, direct, and circular addressing modes.
4. Control Registers
12 Control Registers:
Include status registers (flags), program counters, stack pointers, etc
Used to manage interrupts, exceptions, and processor state.
Address Generation Units (AGUs)
Address Generation 0 & 1:
• Allow two memory accesses per cycle (load/store) in parallel with
computation.
• Provide indirect, direct, and circular addressing modes.
DMA Coprocessor
This block operates independently of the CPU, allowing parallel data
transfer.
Functions:
• Transfers data between memory blocks or between memory and
peripherals (like serial ports).
• Offloads data movement tasks from CPU, increasing overall system
performance.
COMPONENTS
Address Generation:
• Automatically calculates source and destination addresses during
transfers.
Control Registers:
• Configure block sizes, transfer modes, and initiate or stop transfers.
Memory Subsystem
Program Cache (64 × 32 bits):
Stores recently fetched instructions to reduce wait times. Improves execution
speed by reducing instruction fetch from slower memory.
RAM Blocks:
RAM Block 0 (1k × 32): Can be used for code or data. Faster access due to on-
chip integration.
RAM Blocks 1 & 2 (256 × 32 each): Smaller blocks for buffers or stack. Can
be mapped differently depending on the application.
• ROM (4k × 32):Stores boot code, diagnostics, or fixed functions.
• Non-volatile; not modifiable during execution.
EXPANSION PORT (C30)
Features
• 32-bit interface to external memory or peripherals.
• Allows the system to grow by connecting to off-chip RAM, ROM, or memory-
mapped devices.
• Can be used to load large programs or data sets.
Primary port memory interface
• These interfaces provide access to external memory or peripherals.
Types:
• Data Access: Supports 8, 16, or 32-bit data access depending on DSP
version (C30, C31, C32).
• Program Access: Separate access for instructions for better performance.
• Control Signals: Include signals like STRB, RDY, HOLD, etc., to
manage bus operations and handshaking.
Timers (Timer 0 & Timer 1)
Functions:
• Generate time delays. Measure time intervals. Trigger interrupts at precise intervals
for periodic tasks.
Serial Ports (0 & 1)
Purpose: Used for serial communication (SPI-like).Connects to other DSPs, ADCs,
DACs, or sensors. Features: Full-duplex operation, Programmable baud rate and
word length, DMA-compatible for high-speed data transfers.
Controller block
• Handles processor initialization, system control, and interrupts.
Key Signals:
• RESET: Resets the processor to initial state.
• INT3–INT1: External interrupt inputs.
• IACK: Interrupt acknowledge.
• XF1–XF0: User-defined output flags for signaling status.
• CLKIN/X2: Clock input for timing.
• MCBL/MP: Mode control or bus request.
• SHZ, X1, VDD, VSS: Power, oscillator, and control signals.
Block Repeat Registers (RE, RS) and
Repeat Count (RC)
• The block repeat start address, end-address and repeat counter registers
are 32 bits in size.
• RS Contains starting address and end address register.
• RE Contains end address of the block of program memory to be repeated
• If the RC has the number n, the block is executed n+1 times.
Program counter (PC) and Instruction
Register (IR)
• These are 32-bit register and they are not in the register file.
• The PC contains the address of the next instruction to be fetched.
• The IR holds the instruction op-code during the decode phase of the
instruction.
• The Register is used by the instruction decode control circuitry and is not
accessible in the CPU.
