Course Project Title: Design, simulation
& verification of function using Cadence
Virtuoso Tool
VLSI Circuit Design
Sec: A
Group: 5
Course Teacher: DR. SHAHRIYAR MASUD RIZVI
Assistant Professor
Department of Electrical and Electronic Engineering
Submitted by,
#Sl Name ID
1. Md. Robiul Islam Roman 22-46490-1
2. Abrar Asif 22-46270-1
3. MD. FUYAD EBNE RABBY PLABON 22-46309-1
Objectives of the Work
• The prime objective of this project was to design a given
function using cadence virtuoso tool by considering a certain
Eular path.
• After designing schematic, Physical layout was created and
DRC, LVS was checked. Then transient simulation was done.
Working Method TRUTH TABLE:
CMOS LOGIC:
Working Method
All possible Eular’s Path
• A-B-D-C
• A-C-D-B
• B-D-C-A
• B-A-C-D
• C-D-B-A
• C-A-B-D
• D-B-A-C
• D-C-A-B
Desired eular’s path : C-D-B-A
Stick Diagram:
Schematic:
Symbol:
SETUP
Transient
analysis:
Transient
analysis:
For The Delay:
Average Rise Time =
Fall Time:
∴ 𝐴𝑣𝑒𝑟𝑎𝑔𝑒 Rise 𝑇𝑖𝑚𝑒 = 27.165p s
1st Fall time = 9.58p s
∴ Total Delay = Average Rise Time + Average Fall
2nd Fall time = 17.65p s
3rd Fall Time = 17.68p s Time
4th Fall Time =9.72 p s Total Delay = 13.66p s + 27.165p s
𝑇𝑜𝑡𝑎𝑙 𝐷𝑒𝑙𝑎𝑦 = 40.8225 ps
Average Fall Time =
∴ 𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝐹𝑎𝑙𝑙 𝑇𝑖𝑚𝑒 = 13.66p s
Rise Time:
1st Rise time = 30.46p s
2nd Rise time = 27.34p s
3rd Rise Time = 20.33p s
4th Rise Time = 30.53p s
Power Consumptions: Static Power:
Dynamic Power: The value Of Output current during transistor constant Mode :
The value Of Output current during transistor switching 1st Value of current = |-11.78| µA
1st Value of current = |67.28 | µA 2nd Value of current = |-6.48| µA
2nd Value of current = |-114.71 | µA 3rd Value of current = |-12.79| µA
3rd Value of current = |81.30| µA 4th Value of current = |-1.09| µA
4th Value of current = |-115.20| µA 5th Value of current = |-11.23| µA
5th Value of current = |98.65 |µA 6th Value of current = |81.08| µA
5th Value of current = |-222.50 |µA
Average Switching Current
Average Switching Current Average Static Power = Iavg_static× 𝑉𝐷𝐷
Here, 𝑉𝐷𝐷 = 1.8 𝑉 and Iavg_static = 24.537 µA
∴ 𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑆𝑡𝑎𝑡𝑖𝑐 𝑃𝑜𝑤𝑒𝑟 = 1.8 𝑉 × 24.537 µA = 44.166
Average Dynamic Power = Iavg × VDD
Here, VDD= 1.8 𝑉 and Iavg = 116.61µA
Average Dynamic Power = 1.8 𝑉 × 116.61 µA = 209.89 µW
Layout:
DRC Test:
LVS TEST:
LVS check :
Comparison Report:
Spice Code:
• * CDL Netlist: *
• * *
• * Cell Name : OBE_Project_G5 *
• * Netlisted : Wed Jun 25 07:14:00 2025 *
• * Pegasus Version: 22.24-s003 Tue Jun 27 17:22:55 PDT 2023 *
• * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
• *.LDD
• *.DEVTMPLT 0 MN(g45n1svt) _nmos1v ndiff_conn(D) poly_conn(G) ndiff_conn(S) psubstrate(B)
• *.DEVTMPLT 1 MP(g45p1svt) _pmos1v pdiff_conn(D) poly_conn(G) pdiff_conn(S) nwell_conn(B)
• * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
• * Sub cell: OBE_Project_G5 *
• * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
• .subckt OBE_Project_G5 A B C D F Vdd Vss
• ** N=10 EP=7 FDC=8
• M0 9 C F Vss g45n1svt L=4.5e-08 W=2.4e-07 AD=1.44e-14 AS=3.36e-14 PD=6e-07 PS=7.6e-07 fw=2.4e-07 sa=1.4e-07 sb=5.55e-07 sca=3.52678 scb=0.000111658
scc=3.66286e-09 $X=2440 $Y=1150 $dt=0
• M1 Vss D 9 Vss g45n1svt L=4.5e-08 W=2.4e-07 AD=3.84e-14 AS=1.44e-14 PD=8e-07 PS=6e-07 fw=2.4e-07 sa=2.45e-07 sb=4.5e-07 sca=3.52678 scb=0.000111658
scc=3.66286e-09 $X=2650 $Y=1150 $dt=0
• M2 10 B Vss Vss g45n1svt L=4.5e-08 W=2.4e-07 AD=1.44e-14 AS=3.84e-14 PD=6e-07 PS=8e-07 fw=2.4e-07 sa=4.5e-07 sb=2.45e-07 sca=3.52678 scb=0.000111658
scc=3.66286e-09 $X=3060 $Y=1150 $dt=0
• M3 F A 10 Vss g45n1svt L=4.5e-08 W=2.4e-07 AD=3.36e-14 AS=1.44e-14 PD=7.6e-07 PS=6e-07 fw=2.4e-07 sa=5.55e-07 sb=1.4e-07 sca=3.52678 scb=0.000111658
scc=3.66286e-09 $X=3270 $Y=1150 $dt=0
• M4 F C 7 Vdd g45p1svt L=4.5e-08 W=2.9e-07 AD=4.64e-14 AS=4.06e-14 PD=9e-07 PS=8.6e-07 fw=2.9e-07 sa=1.4e-07 sb=7.55e-07 sca=74.3415 scb=0.0548179
scc=0.00838497 $X=2030 $Y=4420 $dt=1
• M5 7 D F Vdd g45p1svt L=4.5e-08 W=2.9e-07 AD=4.64e-14 AS=4.64e-14 PD=9e-07 PS=9e-07 fw=2.9e-07 sa=3.45e-07 sb=5.5e-07 sca=60.4964 scb=0.0376719
scc=0.00582505 $X=2440 $Y=4420 $dt=1
• M6 Vdd B 7 Vdd g45p1svt L=4.5e-08 W=2.9e-07 AD=4.64e-14 AS=4.64e-14 PD=9e-07 PS=9e-07 fw=2.9e-07 sa=5.5e-07 sb=3.45e-07 sca=60.4964 scb=0.0376719
scc=0.00582505 $X=2850 $Y=4420 $dt=1
• M7 7 A Vdd Vdd g45p1svt L=4.5e-08 W=2.9e-07 AD=4.06e-14 AS=4.64e-14 PD=8.6e-07 PS=9e-07 fw=2.9e-07 sa=7.55e-07 sb=1.4e-07 sca=74.3415 scb=0.0548179
scc=0.00838497 $X=3260 $Y=4420 $dt=1
Results and Discussions
The physical layout consists of Metal1 and Metal2 routing, diffusion regions, polysilicon gates, and vias, with
visible Vdd and Vss power rails. Input signals A, B, C, and D are arranged following an Euler path, facilitating
efficient connections without shorts.
DRC and LVS was checked for the circuit.
Transient analysis gives waveform of input and output.
Conclusions
In CMOS VLSI design, the process begins with creating a schematic
that defines circuit functionality. The layout is designed by
considering necessary steps and DRC, LVS was checked. Transient
analysis was done to obtain waveform.
Thank You.
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