DD&CO

Faculty: Dr. Bhat Geetalaxmi Jairam

Professor, ISE, NIE, Mysuru
 UNIT – IV

The Processor
BASIC OPERATIONAL CONCEPT
 BASIC OPERATIONAL CONCEPT
• In addition to the ALU and the control circuitry, the processor contains a
number of registers used for several different purposes.
• The instruction register (IR) holds the instruction that is currently being
executed.
• Its output is available to the control circuits, which generate the timing
signals that control the various processing elements involved in executing
the instruction.
• The program counter (PC) is another specialized register. It keeps track
of the execution of a program. It contains the memory address of the next
instruction to be fetched
• During the execution of an instruction, the contents of the PC are updated
to correspond to the address of the next instruction to be executed. It is
customary to say that the PC points to the next instruction that is to be
fetched from the memory and executed.
• Besides the IR and PC, Figure 1.2 shows n general-purpose registers, Ro
through Rn-1
 BASIC OPERATIONAL CONCEPT
Finally, two registers facilitate communication with the memory.
• These are the memory address register (MAR) and the memory data
register (MDR).
• The MAR holds the address of the location to be accessed.
• The MDR contains the data to be written into or read out of the
addressed location.
 Fundamental concepts
• To execute a program, the processor fetches one instruction at a time and
performs the operations specified. Instructions are fetched from successive
memory locations until a branch or a jump instruction is encountered.
• The processor keeps track of the address of the memory location
containing the next instruction to be fetched using the program counter,
PC.
• After fetching an instruction, the contents of the PC are updated to point to
the next instruction in the sequence. A branch instruction may load a
different value into the PC.
• Another key register in the processor is the instruction register, IR.
Suppose that each instruction comprises 4 bytes, and that it is stored in one
memory word.
 Fundamental concepts
To execute an instruction, the processor has to perform the following three
steps:

content IR <- (PC)

address
Instruction size = one word
PC<- PC+4
(4 byte)

• ln cases where an instruction occupies more than one word, steps l and 2
must be repeated as many times as necessary to fetch the complete
instruction.
• These two steps are usually referred to as the fetch phase; step 3 constitutes
the execution phase.
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

x
 BASIC OPERATIONAL CONCEPT
Input and output gating for the registers in Figure 7.1.
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

• To study these operations in detail, we first need to examine the internal

organization of the processor.
• Figure 7.1 shows an organization in which the arithmetic and logic unit
(ALU) and all the registers are interconnected via a single common bus.
• This bus is internal to the processor and should not be confused with the
external bus that connects the processor to the memory and I/O devices.
• The data and address lines of the external memory bus are shown in Figure
7.1 connected to the internal processor bus via the memory data register,
MDR, and the memory address register, MAR, respectively. Register MDR
has two inputs and two outputs.
• Data may be loaded into MDR either from the memory bus or from the
internal processor bus. The data stored in MDR may be placed on either
bus. The input of MAR is connected to the internal bus, and its output is
connected to the external bus and its output is connected to the external
bus.
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

• The control lines of the memory bus are connected to the

instruction decoder and control logic block. This unit is
responsible for issuing the signals that control the operation
of all the units inside the processor and for interacting with
the memory bus.
• The number and use of the processor registers RO through
R(n - 1) vary considerably from one processor to another.
Registers may be provided for general-purpose use by the
programmer. Some may be dedicated as special-purpose
registers, such as index registers or stack pointers.
• Three registers, Y, Z, and TEMP are used by the processor for
temporary storage during execution of some instructions.
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

• The multiplexer MUX selects either the output of register Y or

a constant value 4 to be provided as input A of the ALU. The
constant 4 is used to increment the contents of the program
counter.
• As instruction execution progresses, data are transferred from
one register to another, often passing through the ALU to
perform some arithmetic or logic operation.
• The instruction decoder and control logic unit is responsible
for implementing actions specified by the instruction loaded
in the IR register. The decoder generates the control signals
needed to select the registers involved and direct the transfer
of data. The registers, ALU, and the interconnecting bus are
collectively referred to as the datapath.
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

With few exceptions, an instruction can be executed by

performing one or more of the following operations in some
specified sequence:
• Transfer a word of data from one processor register to
another or to the ALU
• Perform an arithmetic or a logic operation and store the
result in a processor register
• Fetch the contents of a given memory location and load them
into a processor register
• Store a word of data from a processor register into a given
memory location
 BASIC OPERATIONAL CONCEPT
7.1.1 REGISTER TRANSFER
Suppose that we wish to transfer the contents of register RI to register R4.
This can be accomplished as follows:
• Enable the output of register RI by setting R1out to 1. This places the
contents of RI on the processor bus.
• Enable the input of register R4 by setting R4in.to 1. This loads data from
the processor bus into register R4.
 BASIC OPERATIONAL CONCEPT
7.1.1 REGISTER TRANSFER
• An implementation for one bit of register Ri is shown in Figure 7.3

• A two-input multiplexer is used to select the data applied to the input of an

edge-triggered D flip-flop. When the control input Ri in is equal to I, the
multiplexer selects the data on the bus. This data will be loaded into the
flip-flop at the rising edge of the clock.
• When Ri in is equal to 0, the multiplexer feeds back the value currently
stored in the flip-flop.
 BASIC OPERATIONAL CONCEPT
7.1.1 REGISTER TRANSFER
• The Q output of the flip-flop is connected to the bus via a tri-state gate.
When Ri out Is equal to 0, the gate's output is in the high-impedance
(electrically disconnected) state. This corresponds to the open-circuit state
of a switch. When Ri out = l, the gate drives the bus to 0 or 1, depending on
the value of Q.
 BASIC OPERATIONAL CONCEPT
7.1.2 Performing Arithmetic and Logic operation
• The ALU is a combinational circuit that has no internal storage. It performs
arithmetic and logic operations on the two operands applied to its A and B inputs.
• In Figures 7.1 and 7.2, one of the operands is the output of the multiplexer MUX
and the other operand is obtained directly from the bus.
• The result produced by the ALU is stored temporarily in register Z. Therefore, a
sequence of operations to add the contents of register Rl to those of register R2
and store the result in register R3 is
 Fundamental concepts
Single-bus organization of the datapath inside a processor.

9
 BASIC OPERATIONAL CONCEPT
7.1.3 Fetching a Word from memory
• To fetch a word of information from memory, the processor has to specify the
address of the memory location where this information is stored and request a
Read operation.
• The connections for register MDR are illustrated in Figure 7.4. It has four control
signals: MDR in and MDR out control the connection to the internal bus, and MDR in E
and MDR out E control the connection to the external bus.
 BASIC OPERATIONAL CONCEPT
7.1.3 Fetching a Word from memory
• As an example of a read operation, consider the instruction Move (Rl),R2. The actions needed to
execute this instruction are:

This means that the memory read operation requires three steps, which can be described by the signals
being activated as follows:

where WMFC is the control signal that causes the processor's control circuitry to wait for the arrival of the
MFC signal. To accommodate the variability in response time, the processor waits until it receives an
indication that the requested Read operation has been completed
 BASIC OPERATIONAL CONCEPT
7.1.3 Fetching a Word from memory
• Timing of memory Read operation.
 BASIC OPERATIONAL CONCEPT
7.1.3 Fetching a Word from memory
• A Read control signal is activated at the same time MAR is loaded. This signal will
cause the bus interface circuit to send a read command, MR, on the bus.
• With this arrangement, we have combined actions I and 2 above into a single
control step.
• Actions 3 and 4 can also be combined by activating control signal MDRinE while
waiting for a response from the memory.
• Thus, the data received from the memory are loaded into MDR at the end of the
clock cycle in which the MFC signal is received.
• In the next clock cycle, MDRout is activated to transfer the data to register R2.
• Figure 7.5 shows that MDRinE is set to I for exactly same period as the read
command, MR.
 BASIC OPERATIONAL CONCEPT
7.1.34 Storing Word in memory

• Writing a word into a memory location follows a similar procedure. The desired
address is loaded into MAR. Then, the data to be written are loaded into MDR, and
a Write command is issued.
• As in the case of the read operation, the Write control signal causes the memory
bus interface hardware to issue a Write command on the memory bus.
• The processor remains instep 3 until the memory operation is completed and an
MFC response is received.
• Hence, executing the instruction Move R2,(R1) requires the following sequence:
 BASIC OPERATIONAL CONCEPT
7.2 Execution of Complete Instruction
• Let us now put together the sequence of elementary operations required to
execute one instruction.
Add (R3), R1
• Consider the instruction which adds the contents of a memory location pointed to
by R3 to register R1. Executing this instruction requires the following actions:
1 . Fetch the instruction.
2. Fetch the first operand (the contents of the memory location pointed to by R3).
3. Perform the addition.
4. Load the result into Rl.
 BASIC OPERATIONAL CONCEPT
7.2 Execution of Complete Instruction
• Let us now put together the sequence of elementary operations required to
execute one instruction.
Add (R3), R1
• Figure 7.6 gives the sequence of control steps required to perform these
operations for the single-bus architecture of Figure 7.1. Instruction execution
proceeds as follows. Instep 1, the instruction fetch operation is initiated by loading
the contents of the PC into the MAR and sending a Read request to the memory.
The Select signal is set to Select4, which causes the multiplexer MUX to select the
constant 4.
• This value is added to the operand at input B, which is the contents of the PC, and
the result is stored in register Z. The updated value is moved from register Z back
into the PC during step 2, while waiting for the memory to respond. In step 3, the
word fetched from the memory is loaded into the IR.
• Steps 1 through 3 constitute the instruction fetch phase, which is the same for all
instructions. The instruction decoding circuit interprets the contents of the IR at
the beginning of step 4
 BASIC OPERATIONAL CONCEPT
7.2Execution of Complete Instruction
• This enables the control circuitry to activate the control signals for steps 4 through
7, which constitute the execution phase. The contents of register R3 are
transferred to the MAR in step 4 and a memory read operation is initiated.
• Then the contents of RI are transferred to register Y in step 5, to prepare for the
addition operation. When the Read operation is completed, the memory operand
is available in register MDR, and the addition operation is performed in step 6.
• The contents of MDR are gated to the bus, and thus also to the B input of the ALU,
and register Y is selected as the second input to the ALU by choosing Select Y. The
sum is stored in register Z, then transferred to RI in step 7. The End signal causes a
new instruction fetch cycle to begin by returning to step I.