Computer System

Architecture(CSA)
DU # 2101CS602

Unit-2
Basic Computer
Organization and
Design

Prof. Vishal Kansagara

Computer Engineering
Department
Darshan Institute of Engineering & Technology
[email protected]
8200601076
 Looping
Outline
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory-Reference Instructions
• Input-output and Interrupt
• Complete Computer Description
• Design of Accumulator Unit
• Questions Asked in GTU Exam
Instruction Codes
Section - 1
Instruction Codes
 Program
 A program is a set of instructions that specify the operations, operands and the
sequence by which processing has to occur.
 Computer Instruction
 A computer instruction is a binary code that specifies a sequence of micro-operations
for the computer.
 The computer reads each instruction from memory and places it in a control register.
 The control then interprets the binary code of the instruction and proceeds to
execute it by issuing a sequence of micro-operations.
 Instruction Code
 An instruction code is a group Unique
of bits that instruct the
ADD Binary
computer to perform a specific
operation. code is
1547 assigned to
 Example every Opcode
 Operation Code (Opcode)
 The operation code of an instruction is a group of bits that define such operations as
add, subtract, multiply, shift, and complement.
 The number of bits required for the operation code of an instruction depends on the
total
Prof. Vishalnumber
J. Kansagara of operations available
#2101CS602 (CSA)  Unitin the Computer
2 -Basic computer.
Organization and Design 4
Stored Program Organization

Memory
4096 x 16

1 1 1 0
5
Opcode
2 1
Address
Instructions
(program)
Instruction
Format
1 0 Operand
5 (data)
Binary Operand

Processor
Register
(accumulator or
AC)

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 5
Stored Program Organization
 The simplest way to organize a computer is to have one processor
register(AC) and an instruction code format with two parts.
 The first part specifies the operation (opcode) to be performed and the second
specifies an address (operand).
 The memory address tells the control where to find an operand in memory.
 This operand is read from memory and used as the data to be operated on
together with the data stored in the processor register.
 Instructions are stored in one section of memory and data in another.
 For a memory unit with 4096 words, we need 12 bits to specify an address
since 212 = 4096.
 If we store each instruction code in one 16-bit memory word, we have
available four bits for operation code (opcode) to specify one out of 16
possible operations, and 12 bits to specify the address of an operand.
 The control reads a 16-bit instruction from the program portion of memory.
 It then executes the operation specified by the operation code.
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 6
Instruction format of basic computer

Instruction Format
1 1 1 1 0
5 4Opcod
2 1
I Address
e

0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1
Add Instruction – ADD 457

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 7
Direct & Indirect Addressing of Memory
 If the second part of an
Memory Memory
instruction format
AD AD
2 0 457 3 1 300 specifies the address of
D D
2 5 an operand, the
instruction is said to
300 1350 have a direct address.
45 Operand  In Indirect address,
7 135 Operand the bits in the second
0 part of the instruction
designate an address of
a memory word in which
+ + the address of the
operand is found.

AC AC

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 8
Direct & Indirect Addressing of Memory
1 1 1 1 0 1 1 1 1 0
5 4 2 1 5 4 2 1
2 0 ADD 457 3 1 ADD 300
2 5
 A direct address instruction is  The instruction in address 35 has a
placed at address 22 in memory. mode bit I = 1, recognized as an
 The I bit is 0, so the instruction is indirect address instruction.
recognized as a direct address  The address part is the binary
instruction. equivalent of 300.
 The opcode specifies an ADD  The control goes to address 300 to
instruction, and the address part is find the address of the operand.
the binary equivalent of 457.  The address of the operand in this
 The control finds the operand in case is 1350.
memory at address 457 and adds  The operand found in address
it to the content of AC. 1350 is then added to the content
of AC.
Prof. Vishal J. Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 9
Computer Registers
Section - 2
Computer Registers
1 0 1 0
1 Program 5 Accumulator(
PC Counter(12)
Holds address of instruction AC 16)
Processor register
executed next
1 0 7 0
1 Address Output
AR Register(12)
Holds address for memory OUTR Register(8)
Holds output character
1 0 7 0
5 Instruction Input
IR Register(16)
Holds instruction code INPR Register(8)
Holds input character
1 0
5
TR Temporary Memory
Register(16)
Holds temporary data
4096 words
1 0
5 Data 16 bits per word
DR Register(16)
Holds memory operand

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 11
 1 S
0 S Bu
Common
2
Memory 0 S
1 s
4096 x 16 0 7

Bus System
Addres
Writ Rea s
e AR d 1

of Basic L
D
INR CL
PC R 2

Computer AC
L INR CL
D DR R 3
1L INR CL
Adder E D R
& AC 4
Logic
L INR CL
D R
INPR
DR
IR 5
AC
L
AC D TR 6
DR L INR CL
R
D OUTR
Clock
L
D AC
Computer Instructions
Section - 3
Types of Computer Instructions
1. Memory Reference Instruction
1 1 1 1 0
5 4Opcod
2 1
I Address
e

0
1 0
1 0
1 0
1 Address

0xxx 8xxx ANDAND the content of memory to AC

1xxx 9xxx ADDAdd the content of memory to AC
2xxx Axxx LDA Load memory word to AC
3xxx Bxxx STAStore content of AC in memory
4xxx Cxxx BUNBranch unconditionally
5xxx Dxxx BSABranch and save return address
6xxx Exxx ISZ Increment and skip if zero
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 14
Types of Computer Instructions
2. Register Reference Instruction
1 1 1 1 1 0
5 4 3 2 1
0 1 1 1 Register Operation

0 1 1 1 0 1
1 0 0 0
1 1 0 0
1 1 0
1 0 0 0 0 0

7800 CLA Clear AC

7400 CLE Clear E
7200 CMA Complement AC
7100 CME Complement E
7080 CIR Circulate right AC and E
7040 CIL Circulate left AC and E
7020 INC Increment AC
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 15
Types of Computer Instructions
2. Register Reference Instruction

1 1 1 1 1 0
5 4 3 2 1
0 1 1 1 Register Operation

0 1 1 1 0 0 0 0 0 0 0 1
0 0 0
1 1 0
1 0
1

7010 SPASkip next instruction if AC is positive

7008 SNASkip next instruction if AC is negative
7004 SZASkip next instruction if AC is zero
7002 SZESkip next instruction if E is zero
7001 HLT Halt computer

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 16
Types of Computer Instructions
3. Input – Output Instruction
1 1 1 1 1 0
5 4 3 2 1
1 1 1 1 I/O Operation

1 1 1 1 1
0 0 0
1 1 0
1 0
1 0
1 0 0 0 0 0 0

F800 INP Input character to AC

F400 OUTOutput character from AC
F200 SKI Skip on input flag
F100 SKO Skip on output flag
F080 ION Interrupt on
F040 IOF Interrupt off

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 17
Instruction Set Completeness
 Instruction set is said to be complete if it includes enough instructions in
each of the following categories:
1. Arithmetic, logical and shift instructions
2. Instructions for moving information to and from memory and processor registers
3. Program control instructions together with instructions that check status conditions
4. Input and output instructions

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 18
Timing and Control
Section - 4
Control Unit of Basic Computer
0 0 0 1 010001010111
Instruction
Register Other
1 inputs
14 13 12 11 - 0
5
0 0 0 1
3x8
Decoder
7 6 5 4 3 2 Contro
1 0
D Control l O/p
I D D
0
Logic
Gates
1 7

T1
T0
5
15 14 ... 2
1 0 4 x 16
Decoder

4-bit sequence Increment

Clear
counter (SC) Cloc(INR)
(CLR)
k
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 20
Control Unit
 Components of Control unit are
1. Two decoders
2. A sequence counter
3. Control logic gates
 An instruction read from memory is placed in the instruction register (IR).
 In control unit the IR is divided into three parts: I bit, the operation code
(12-14)bit, and bits 0 through 11.
 The operation code in bits 12 through 14 are decoded with a 3 x 8
decoder.
 Bit-15 of the instruction is transferred to a flip-flop designated by the
symbol I.
 The eight outputs of the decoder are designated by the symbols D0
through D7.
 Bits 0 through 11 are applied to the control logic gates.
 TheProf.4‐bit sequence #2101CS602
Vishal Kansagara counter(CSA)can count
 Unit in binary
2 -Basic Computer from
Organization 0 through 15.
and Design 21 The
Control Unit
 Most of the time, the counter is incremented to provide the sequence of
timing signals out of 4 X 16 decoder.
 Once in awhile, the counter is cleared to 0, causing the next timing signal
to be T0.
 As an example, consider the case where SC is incremented to provide
timing signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to
0 if decoder output D3 is active. This is expressed symbolically by the
statement
D3T4: SC ← 0
 Initially, the CLR input of SC is active.
 The first positive transition of the clock clears SC to 0, which in turn
activates the timing T0 out of the decoder.
 T0 is active during one clock cycle.
 The positive clock transition labeled T0 in the diagram will trigger only
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 22
Timing Cycle for D3T4: SC ← 0
𝑇0 𝑇1 𝑇2 𝑇3 𝑇4 𝑇5
Clock

𝑇0
𝑇1

𝑇2

𝑇3
𝑇4
𝐷3
CLR
SC

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 23
Control Unit
 SC is incremented with every positive clock transition, unless its CLR input
is active.
 This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and so
on. If SC is not cleared, the timing signals will continue with T 5, T6, up to
T15 and back to T0.
 The last three waveforms shows how SC is cleared when D3T4 = 1.
 Output D3 from the operation decoder becomes active at the end of timing
signal T2.
 When timing signal T4 becomes active, the output of the AND gate that
implements the control function D3T4 becomes active.
 This signal is applied to the CLR input of SC.
 On the next positive clock transition the counter is cleared to 0.
 This causes the timing signal T0 to become active instead of T5 that would
have been
Prof. Vishal active if SC
Kansagara were(CSA)
#2101CS602 incremented instead
 Unit 2 -Basic Computer ofandcleared.
Organization Design 24
Control Organization
 Hardwired Control
 The control logic is implemented with gates, flips-flops, decoders and other digital
circuits.
 It can be optimized to produce a fast mode of operation.
 It requires changes in the wiring among the various components if the design has to
be modified or changed.
 Microprogrammed Control
 The control information is stored in a control memory.
 The control memory is programmed to initiate the required sequence of micro-
operations.
 Any required changes or modifications can be done by updating the microprogram in
control memory.

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 25
Instruction Cycle
Section - 5
Instruction Cycle
 A program residing in the  Fetch & Decode
memory unit of the computer  PC is loaded with the address of the
consists of a sequence of first instruction in the program.
instructions. In the basic  The micro-operations for fetch and
computer each instruction cycle decode phases are as follows:
consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from  Determine the type of instruction
memory if the instruction has an
 During time , the control unit determines
indirect address.
the type of instruction i.e. Memory
4. Execute the instruction. reference, Register reference or Input-
 After step 4, the control goes Output instruction.
 If then instruction must be register
back to step 1 to fetch, decode reference or input-output else memory
and execute the next instruction. reference instruction.
 This process continues unless a
HALT instruction is encountered.
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 27
 SC ← 0
Start

𝑇0
AR ← PC

IR ← M[AR], PC ←
𝑇1
PC + 1
𝑇2
Decode operation code in

AR ← IR(0-11), I ← IR(15)
IR(12-14)

(Register or I/O) = 1 D = 0 (Memory-reference)

7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

Execute𝑇 3 𝑇3 𝑇3
AR ←
Execute 𝑇3
input- Nothin
register-
output M[AR] g
reference
instructio
SC ← 0
instruction
SC ← 0
n
Execute
memory-reference

SC ← 0
instruction

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 28
Memory-Reference
Instructions
Section - 6
Memory Reference Instructions
1. AND: AND to AC
This is an instruction that performs the AND logic operation on pairs of
bits in AC and the memory word specified by the effective address. The
result of the operation is transferred to AC.
D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
2. ADD: ADD to AC
This instruction adds the content of the memory word specified by the
effective address to the value of AC. The sum is transferred into AC and
the output carry Cout is transferred to the E (extended accumulator) flip-
flop.
D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 30
Memory Reference Instructions
3. LDA: Load to AC
This instruction transfers the memory word specified by the effective
address to AC.
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

4. STA: Store AC
This instruction stores the content of AC into the memory word specified
by the effective address.
D3T4: M[AR]  AC, SC  0

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 31
Memory Reference Instructions
5. BUN: Branch Unconditionally
This instruction transfers the program to instruction specified by the
effective address. The BUN instruction allows the programmer to specify
an instruction out of sequence and the program branches (or jumps)
unconditionally.
D4T4: PC  AR, SC  0

6. BSA: Branch and Save Return Address

This instruction is useful for branching to a portion of the program called
a subroutine or procedure. When executed, the BSA instruction stores
the address of the next instruction in sequence (which is available in PC)
D5T4: M[AR]
into a memory location PC,theAR
 by
specified  AR +
effective 1
address.
D5T5: PC  AR, SC  0

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 32
Memory Reference Instructions (BSA)

0 BSA 0 BSA
20 20
135 135
PC = 21 Next Instruction 21 Next Instruction

AR = 135 135 2
136 PC = 136 1

Subroutine Subroutine

1 BUN 1 BUN
135 135
Memory, PC and AR at Memory and PC after
Time T4 execution

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 33
Memory Reference Instructions
7. ISZ: Increment and Skip if Zero
These instruction increments the word specified by the effective address,
and if the incremented value is equal to 0, PC is incremented by 1. Since
it is not possible to increment a word inside the memory, it is necessary
to read the word into DR, increment DR, and store the word back into
memory.

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 34
 Register Reference Instruction
I’T3 = r (common to all register reference instructions)

CLA rB11 AC ← 0
IR(i) = Bi [bit in IR(0-11) that specifies the operation]
Clear AC
E←0
AC ← AC’
CLE rB10 Clear E

E ← E’
CMA rB9 Complement AC

rB7 AC ← shr AC, AC(15) ← E, E ← AC(0)

CME rB8 Complement E

rB6 AC ← shl AC, AC(0) ← E, E ← AC(15)

CIR Circulate right

rB5 AC ← AC + 1
CIL Circulate left
INC Increment AC
SPA rB4 If (AC(15) = 0) then (PC ← PC + 1) Skip if AC is positive
SNA rB3 If (AC(15) = 1) then (PC ← PC + 1) Skip if AC is negative
If (AC = 0) then (PC ← PC + 1)
If (E = 0) then (PC ← PC + 1)
SZA rB2 Skip if AC is zero
SZE rB1 Skip if E is zero
HLT rB0 S ← 0 (S is a start-stop flip-flop) Halt Computer

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 35
Input-output and
Interrupt
Section - 7
Input-Output of basic computer

Input-Output Serial Computer

terminal communicati registers and
on interface flip-flop
FGO =1
=0

Receiver
Printer OUTR
Interface

AC

Transmitter
Keyboard INPR
Interface

FGI =0=1

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 37
Input-Output of basic computer
 A computer can serve no useful purpose unless it communicates with the
external environment.
 To exhibit the most basic requirements for input and output
communication, we will use a terminal unit with a keyboard and printer.
 The terminal sends and receives serial information and each quantity of
information has eight bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input register
INPR.
 The serial information for the printer is stored in the output register OUTR.
 These two registers communicate with a communication interface serially
and with the AC in parallel.

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 38
Process of input & output information transfer
Input Output
Transfer
 Initially, the Transfer
input flag FGI is  The output register OUTR works
cleared to 0. When a key is struck similarly but the direction of
in the keyboard, an 8-bit information flow is reversed.
alphanumeric code is shifted into  Initially, the output flag FGO is set
INPR and the input flag FGI is set to to 1. The computer checks the flag
1. bit; if it is 1, the information from
 As long as the flag is set, the AC is transferred in parallel to
information in INPR cannot be OUTR and FGO is cleared to 0. The
changed by striking another key. output device accepts the coded
The computer checks the flag bit; if information, prints the
it is 1, the information from INPR is corresponding character, and when
transferred in parallel into AC and the operation is completed, it sets
FGI is cleared to 0. FGO to 1.
 Once the flag is cleared, new  The computer does not load a new
information can be shifted into INPR character into OUTR when FGO is 0
by striking another key.
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basicbecause this
Computer Organization condition indicates
and Design 39
 Input-Output Instruction
D7IT3 = p (common to all input-output instructions)

pB11 AC(0-7) ← INPR, FGI ← 0

IR(i) = Bi [bit in IR(6-11) that specifies the operation]

pB10 OUTR ← AC(0-7), FGO ← 0

INP Input Character
OUT Output Character
SKI pB9 If (FGI = 1) then (PC ← PC + 1) Skip on input flag
SKO pB8 If (FGO = 1) then (PC ← PC + 1) Skip on output flag
IEN ← 1
IEN ← 0
ION pB7 Interrupt enable on
IOF pB6 Interrupt enable off

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 40
Interrupt Cycle

Instruction cycle= 0 = 1Interrupt cycle

R

Store return
Fetch & Decode address in
instruction
M[0] ← PC
location 0
Execute
IE =0
instructio
N Branch to
n
PC ← 1
=1 location 1
=1 FGI

IEN ← 0
=0

R←0
=1 FG
O
R←
=0
1

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 41
Interrupt Cycle
 The interrupt cycle is a hardware implementation of a branch and save
return address operation.
 An interrupt flip-flop R is included in the computer.
 When R = 0, the computer goes through an instruction cycle.
 During the execute phase of the instruction cycle IEN is checked by the
control.
 If it is 0, it indicates that the programmer does not want to use the
interrupt, so control continues with the next instruction cycle.
 If IEN is 1, control checks the flag bits.
 If both flags are 0, it indicates that neither the input nor the output
registers are ready for transfer of information.
 In this case, control continues with the next instruction cycle. If either flag
is set to 1 while IEN = 1, flip-flop R is set to 1.
 At the end of the execute phase, control checks the value of R, and if it is
equal to J.1,
Prof. Vishal it goes to#2101CS602
Kansagara an interrupt cycle
(CSA)  Unit instead
2 -Basic Computer of an
Organization andinstruction
Design cycle.
42
Register transfer statements for Interrupt cycle
 The flip-flop is set to 1 if IEN = 1 and either FGI or FGO are equal to 1. This
can happen with any clock transition except when timing signals T 0, T1 or
T2 are active.
 The condition for setting flip-flop R = 1 can be expressed with the
following register transfer statement:
T0 T1 T2 (IEN) (FGI + FGO): R  1
 The symbol + between FGI and FGO in the control function designates a
logic OR operation. This is AND with IEN and T0 T1 T2.
 The fetch and decode phases of the instruction cycle must be modified
and Replace T0, T1, T2 with R'T0, R'T1, R'T2
 Therefore the interrupt cycle statements are :
RT0 : AR  0, TR  PC
RT1 : M[AR]  TR, PC  0
Prof. Vishal Kansagara RT : PC  PC(CSA)
#2101CS602 + 1, IEN
 Unit 0, R Organization
 Computer
2 -Basic  0, SC and  0
Design 43
Register transfer statements for Interrupt cycle
 During the first timing signal AR is cleared to 0, and the content of PC is
transferred to the temporary register TR.
 With the second timing signal, the return address is stored in memory at
location 0 and PC is cleared to 0.
 The third timing signal increments PC to 1, clears IEN and R, and control
goes back to T0 by clearing SC to 0.
 The beginning of the next instruction cycle has the condition RT0 and the
content of PC is equal to 1. The control then goes through an instruction
cycle that fetches and executes the BUN instruction in location 1.

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 44
Demonstration of Interrupt Cycle

0 0 256
0 BUN 0 BUN
1 PC = 1
1120 1120
255 255
PC = 256 256
Main Program Main Program

1120 1120
I/O program I/O program

1 BUN 1 BUN
0 0
Before Interrupt After Interrupt

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 45
Complete Computer
Description
Section - 8
 Start
SC ← 0, IEN ← 0, R
←0

(Instruction cycle) = 0 =1 (Interrupt cycle)

R

AR ← 0, TR ←
𝑅′𝑇0 𝑅𝑇 0
AR ← PC
PC

IR ← M[AR], PC ← PC M[AR] ← TR, PC

𝑅′𝑇1 𝑅𝑇 1
+1 ←0
𝑅′𝑇2 𝑅𝑇 2
Decode operation code in PC ← PC + 1, IEN

AR ← IR(0-11), I ← IR(15)
IR(12-14) ← 0, R ← 0, SC ←
0

(Register or I/O) = 1 D = 0 (Memory-reference)

7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

AR ←
𝑇
Execute 3 Execute
𝑇3 𝑇3 𝑇3
Nothin
input- register- M[AR] g
output reference

SC ← 0 SC ← 0
instruction instruction

Execute
memory-reference

SC ← 0
instruction
Design of Accumulator
Unit
Section - 9
Design of Accumulator Logic
 In order to design the logic associated with AC, it is necessary to extract
all the statements that change the content of AC.

D0T5: AC  AC  DR, SC  0 AND with DR

D1T5: AC  AC + DR, SC  0 ADD with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7) ← INPR, FGI ← 0 Transfer from INPR
rB9: AC ← AC’ Complement
rB7: AC ← shr AC, AC(15) ← E Shift right
rB6: AC ← shl AC, AC(0) ← E Shift left
rB11: AC ← 0 Clear
rB5: AC ← AC + 1 Increment

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 49
Design of Accumulator Logic

Circuit associated with AC

16
16 Adder and 16 Accumulator 16
From DR
logic circuit register (AC) To bus
8
From INPR

LD INR CLR
Clock

Control gates

Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 50
Design of Accumulator Logic
Gate structure for controlling LD, INR and CLR of AC
D0 AND
T5 16 16
AC
D1 ADD From To bus
Adder
D2 DR & LD INR CLR
T5 Logic
Clock
p
B11 INPR
r CMA
B9

SHR
B7
SHL
B6
INC
B5
CLR
B11
Prof. Vishal Kansagara #2101CS602 (CSA)  Unit 2 -Basic Computer Organization and Design 51


Thank you