UNIT-II

MICROPROCESSOR (8085)
&
MICROCONTROLLER (8051)
 UNIT II
8085 MICROPROCESSOR AND 8051
MICROCONTROLLER

Architecture of 8085 – Pin Configuration – Addressing Modes –

Instruction set, Timing diagram of 8085 – Concepts of 8051

microcontroller – Block diagram,.

Architecture of 8085 microprocessor
 The 8085 and Its Busses
• The 8085 is an 8-bit general purpose microprocessor that can
address 216 =64K Byte of memory.
• It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
– The pins on the chip can be grouped into 6 groups:
• Address Bus.
• Data Bus.
• Control and Status Signals.
• Power supply and frequency.
• Externally Initiated Signals.
• Serial I/O ports.
 Functional Blocks
• Increment/
• Registers
Decrement Address
• ALU Latch
• Instruction • Interrupt Control
Decoder
• Serial I/O Control
• Address Buffer
• Timing and control
• Address/Data circuitry
Buffer
Registers
• General purpose
Registers
• Temporary
Registers
• Special Purpose
Register
• 16 Bit Registers
 The Flags register
– There is also the flags register whose bits are affected by the arithmetic &
logic operations.
• S-sign flag
– The sign flag is set if bit D7 of the accumulator is set after an
arithmetic or logic operation.
CY – 0- + Ve 1- -Ve
• Z-zero flag
P

– Set if the result of the ALU operation is 0. Otherwise is reset. This

flag is affected by operations on the accumulator as well as other
AC

registers. (DCR B).

• AC-Auxiliary Carry
– This flag is set when a carry is generated from bit D3 and passed to
Z

D4 . This flag is used only internally for BCD operations.

S

• P-Parity flag
– After an ALU operation if the result has an even no of 1’s the p-flag
is set. Otherwise it is cleared. So, the flag can be used to indicate
even parity.
• CY-carry flag
– CY = carry is set when result generates a carry. Also a borrow flag.
 PROGRAM COUNTER (PC) AND STACK
POINTER (SP)
• These are two 16-bit registers used to hold memory
addresses.
• PC:
– The function of the PC is to point to the memory address from which
the next byte is to be fetched.
– When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location.
• SP:
– It points to a memory location in R/W memory, called the stack.
– The beginning of the stack is defined by loading a 16-bit address in the
stack pointer.
– The PC will automatically update when calling to /returning from
Subroutines.
 The ALU
• In addition to the arithmetic & logic circuits, the ALU
includes the accumulator, which is part of every
arithmetic & logic operation.

• Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the
operation. This temporary register is not accessible by
the programmer.
The Address and Data Busses
• The address bus has 8 signal lines A8 – A15 which are
unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8
data bits.
– So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7
and D0 – D7 at the same time.
• During the execution of the instruction, these lines carry
the address bits during the early part, then during the
late parts of the execution, they carry the 8 data bits.
– In order to separate the address from the data, we can use a
latch to save the value before the function of the bits
changes.
INCREMENT/ DECREMENT ADDRESS LATCH

Interrupt Control:
Fetch, Decode & execute
RST 5.5, RST 6.5, RST 7.5, TRAP, & INTR
Serial I/O Control
SOD & SID
Timing and Control Circuitry
Its control fetching, decoding, execution
The Control and Status Signals
There are 4 main control and status signals. These are:
• ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 – AD7 lines have an address on
them. It becomes 0 after that. This signal can be used to
enable a latch to save the address bits from the AD lines.
• RD: Read. Active low indicates that the data must be read
from the selected memory location or I/O port via data
bus.
• WR: Write. Active low indicates that the data must be
written into the selected memory location or I/O port via
data bus..
• IO/M: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation
(IO/M=1).
• S1 and S0 : Status signals to specify the kind of operation
being performed .Usually un-used in small systems.
 ADDRESSING MODES
• IMMEDIATE
MVI A,05(H) LXI H,0050(H)
• DIRECT
LDA 0208(H)
• REGISTER
MOV B,C ADD B
• REGISTER INDIRECT
LDAX B
• INHERENT
HLT STC(SET CARRY FLAG)
NOTATIONS MEANING

M Memory location pointed by HL reg pair

r 8- bit register

rp 16-bit register

rs Source register

rd Destination register

addr 16-bit address

Pin configuration of
8085 microprocessor

a) Power supply
b) Frequency signals
c) Data bus
d) Address bus
e) Control bus
f) Interrupt signal
g) Serial I/O signal
h) DMA signal
i) Reset Signal
 Instruction set
Data Transfer Group
• MVI r, data (8- Bit)
• MVI M, data (8- Bit)
• MOV rd, rs
• MOV M, rs
• MOV rd, M
• LXI rp, data (16 bit)
• STA addr
• LDA addr
• SHLD addr
• LHLD addr
• STAX addr
• LDAX rp
• XCHG
• MOV Rd,Rs MOV B,C
• MVI R,8bit MVI A,05H
• LXI Rp,16bit LXI B,2050
• MOV R,M MOV D,M
• MOV M,R MOV M,E
• LDA 16 bit LDA 8005H
• STA 16 bit STA 8006H
• LDAx Rp LDAx B
• STAX Rp STAX D
 ARITHEMATIC GROUP

• ADD r • SUB r • INR r

• ADD M • SUB M • INR M
• ADI data (8) • SUI data • INX rp
• DCR r
• ADC r • SBB r
• DCR M
• ADC M • SBB M • DCX rp
• ACI data (8) • SBI data
• DAD rp • DAA
 LOGIC GROUP
• ANA r • ORI data
• ANA M • CMP r
• ANI data • CMP M
• XRA r • CPI data
• XRA M • STC
• XRI data • CMC
• ORA r • CMA
• ORA M
 BRANCH GROUP
• JUMP INSTRUCTION
• CALL and RETURN INSTRUCTION
• RESTART INSTRUCTION
INSTRUCTION SET
 INSTUCTION SET

MOVEMENT MODIFICATION CONTROL

INSTUCTIONS INSTUCTIONS INSTRUCTIONS

GROUP-0 GROUP – 1 GROUP – 2 GROUP – 3B I/O

ARITHEMATI GROUP -
DATA DATA & MACHINE
TRANSFER TRANSFER C & LOGIC 3A CONTROL
BRANCH

MVI,INR,DCR,LD JNZ,JNC,JC HLT,ENABL

AND,ADD,
A,STA,RAR,CMC, MOV , E,DISABLE,
OR,XOR
CMA,STC,DAA, JZ etc., INTR
etc.,
DAD,LDAX,SHLD, PROGRAM PROCESS
INX,RIM ETC., CONTROL CONTROL
 Static RAM Dynamic RAM
Static RAM contains less memory cells Dynamic RAM contains more memory
per unit area cells as compare to static RAM per unit
area
It has less access time, hence faster Its access time is greater than static
memories RAMs
Static RAM consists of number of flip- Dynamic RAM stores the data as a
flops. Each flip-flop stores one bit charge on the capacitor. It consists of
MOSFET and the capacitor for each cell
Refreshing circuitry is not required Refreshing circuitry is required to
maintain the charge on the capacitor
after every few milliseconds
Cost is more Cost is less
 Timing diagram of 8085

Timing Diagram is a graphical representation. It represents the execution

time taken by each instruction in a graphical format. The execution time
is represented in T-states.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is
called machine cycle.
T-State:
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as
T-state.
 Instruction cycle

Machine cycle1 Machine cycle 2 Machine cycle 5

T – State 1 T – State 2 T – State 3 T – State 6

The 8085 microprocessor has 5 basic machine
cycles. They are
1.Opcode fetch cycle (4T)
2.Memory write cycle (3 T)
3.I/O read cycle (3 T)
4.Memory read cycle (3 T)
5.I/O write cycle (3 T)
• Each instruction of the 8085 processor consists of one to five
machine cycles, i.e., when the 8085 processor executes an
instruction, it will execute some of the machine cycles in a
specific order.

• The processor takes a definite time to execute the machine

cycles. The time taken by the processor to execute a machine
cycle is expressed in T-states.

• One T-state is equal to the time period of the internal clock signal
of the processor.

• The T-state starts at the falling edge of a clock.

• In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal
operations by the processor.
Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch
cycle.
– In this cycle, the microprocessor brings in the instruction’s
Opcode from memory.
• To differentiate this machine cycle from the very similar
“memory read” cycle, the control & status signals are set
as follows:
– IO/M=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in an
opcode fetch machine cycle.
 TIMING DIAGRAM

1.Machine Cycle
2.Opcode fetch
3.Memory read
4.Memory write
5.I/O read
6.I/O write
7.Interrupt ACK
8.Bus idle
 TIMING DIAGRAM
Status Control
S.No Machine Cycle
IO/m S1 S2 RD WR INTA

1 Opcode fetch 0 1 1 0 1 1
 TIMING DIAGRAM
Status Control
S.No Machine Cycle
IO/m S1 S2 RD WR INTA
2 Memory read 0 1 0 0 1 1
 Status Control
S.No Machine Cycle
IO/m S1 S2 RD WR INTA

3 Memory write 0 0 1 1 0 1
 Status Control
S.No Machine Cycle
IO/m S1 S2 RD WR INTA

4 I/O read 1 1 0 0 1 1
 Status Control
S.No Machine Cycle
IO/m S1 S2 RD WR INTA

5 I/O write 1 0 1 1 0 1
Concepts of 8051 microcontroller & Block
diagram
Disadvantages of microprocessor
• The overall system cost is high
• A large sized PCB is required for
assembling all the components
• Overall product design requires
more time
• Physical size of the product is big
• A discrete components are used,
the system is not reliable
Advantages of Microcontroller
based System
• As the peripherals are integrated into a single chip, the overall
system cost is very less
• The product is of small size compared to micro processor based
system
• The system design now requires very little efforts
• As the peripherals are integrated with a microprocessor the
system is more reliable
• Though microcontroller may have on chip ROM,RAM and I/O
ports, addition ROM, RAM I/O ports may be interfaced externally
if required
• On chip ROM provide a software security
 Pin configuration of 8051 microcontroller
a) Power supply
b) Port 0 (P0.0 to P0.7)
c) Port 1(P1.0 to P1.7)
d) Port 2 (P2.0 to P2.7)
e) Port 3 (P3.0 to P3.7)
f) ALE/Prog
g) XTAL1 & XTAL2
h) PSEN
i) EA/VPP
j) RST
Architecture of 8051 microcontroller
Comparison some of the 8051 Family
Members
ROM RAM Timer
8051 4k 128 2
8031 - 128 2
8751 4k 128 2
eprom
8052 8krom 256 3
8032 - 256 3
8752 8k 256 3
eprom
8051 Basic Component
• 4K bytes internal ROM
• 128 bytes internal RAM
• Four 8-bit I/O ports (P0 - P3).
• Two 16-bit timers/counters
• One serial interface
• 64k external memory for code
• 64k external memory for data
• 210 bit addressable
 The basic 8051 Core
• 8-bit CPU optimized for control applications
• Capability for single bit Boolean operations.
• Supports up to 64K of program memory.
• Supports up to 64K of data memory.
• 4 K bytes of on-chip program memory.
• Newer devices provide more.
• 128 or 256 bytes of on-chip data RAM
• Four 8 bit ports.
• Two 16-bit timer/counters
• UART
• Interrupts
• On-chip clock oscillator
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1
Control program Counter
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
 GATE QUESTIONS:
Q1.In an 8085 microprocessor, the instruction CMP B has been executed
while the content of the accumulator is less than that of register B. As a
result

(a) Carry flag will be set but zero flag will be reset.

(b) Carry flag will be reset but zero flag will be set.

(c) Both Carry flag and zero flag will be reset.

(d) Both Carry flag and zero flag will be set

Answer: (a)

Explanation:

CMP B -> the contents of B and A are compared and result is indicated
by flag.
if(A) < B :: Carry flag is set, Zero flag is reset.
if(A) = B :: Zero flag is set, Carry flag is reset.
if(A) > B :: Carry and Zero flags are reset.
Q2.The number of memory cycles required to execute the following 8085
instructions
(I) LDA 3000H
(II) LXI D, F0F1H
would be

(a) 2 for (I) and 2 for (II)

(b) 4 for (I) and 3 for (II)

(c) 3 for (I) and 3 for (II)

(d) 3 for (I) and 4 for (II)

Answer: (b)

Explanation:

Memory cycles
LDA 3000H --> Fetch, Read, Read, Read
--------------- --------
address data

LXI D, F0F1H--> Fetch, Read, Read

Q3.Consider the sequence of 8085 instructions given below:
LXI H, 9258
MOV A, M
CMA
MOV M, A

which one of the following is performed by this sequence?

(a) Contents of location 9258 are moved to the accumulator.

(b) Contents of location 9258 are compared with the contents of accumulator

(c) Contents of location 9258 are complemented and stored in location 9258

(d) Contents of location 5892 are complemented and stored in location 5892
Answer: (c)

Explanation:

LXI H, 9258 => the data is loaded into the Register pair
MOV A, M => The data in the M(9288) is moved to
accumulator
CMA => The Accumulator data is complemented and
stored in
accumulator
MOV M, A => The data in the Accumulator is stored in M.
Q4.It is desired to multiply the numbers 0AH by 0BH and store the result in hte
accumulator. The numbers are available in registers B and C respectively. A
part of the 8085 program for the purpose is given below:

MVI A 00H
Loop;______
____________
____________
HLT END
The sequence of instruction to the complete the program would be.

(a) JNZ LOOP, ADD B, DCR C

(b) ADD B, JNZ LOOP, DCR C
(c) DCR C, JNZ LOOP, ADD B
(d) ADD B, DCR C, JNZ LOOP
Answer: d

Explanation:

The question is to multiply two numbers 0AH and 0BH.

first of all ., In general mathematics the product of 10 and 11 will be equal to 11
times the summation of 10 will be equal to 10 times the summation of 11 which
is equal to 110 (i.e) 10*11=10+10+10+10+10+10+10+10+10+10+10=
11+11+11+11+11+11+11+11+11+11=110.

so the program to multiply 0AH and 0B H will be 0BH times the addition of 0AH
Q5) Why is the speed accessibility of external data memory slower
than internal on-chip RAM?

a. Due to multiplexing of lower order byte of address-data bus

b. Due to multiplexing of higher order byte of address-data bus
c. Due to demultiplexing of lower order byte of address-data bus
d. Due to demultiplexing of higher order byte of address-data bus

ANSWER: (a) Due to multiplexing of lower order byte of address-data

bus