GATE 2026 and ESE 2026
Subject : Computer Organization
by
Dr Y Chakrapani
S E M
Explicit
Normalization
Implicit
Normalization
S E M
Decimal value of a Explicit Normalized
Floating-Point Number
S E M
Decimal value of a Implicit Normalized
Floating-Point Numbers
S E M
Types of Floating-Point Representation
Conventional Floating-Point
Representation
IEEE754 Floating Point
Representation
IEEE754 Single Precision Floating-
Point Representation
IEEE 754 Single Precision
Floating Point Representation
• Single Precision (32 bit) 1+8+23
(a) 1 8 23
Sign of Biased exponent Truncated significand
Mantissa,S (Excess 127 (Mantissa, M)
Exponent)
Value = (-1) s 1.M 2E-127
NUMBER REPRESENTATION
Floating Point Representation (Single Precision)
ve under flow + ve under flow
ve over flow + ve over flow
(2223) 2127 1.0 2-126 0 1.0 2 126 (2223) 2127
IEEE 754 Single Precision Special Number Representation
E(Exponent) M(Mantissa) Number Represented
255 0 Infinite Number
255 0 NaN(Not a number)
1 to 254 Any Value FP Number
0 0 X=(1)s2-126 (0.M)
(Denormalized Form)
0 0 Represents + 0 and 0
E.g., Nan : sqrt (1), , log(-1)
1.0/0.0=1.0/0.0=+, 1.0/0.0=
P1. Represent +10 in IEEE754 Single Precision format
IEEE754 Double Precision Floating-
Point Representation
IEEE 754 Double Precision Floating Point Representation
• Single Precision (64 bit) 1+11+52
(a)
1 11 52
Sign of Biased exponent Truncated significand
Mantissa,S Excess 1023 (Mantissa, M)
Exponent
Value = (-1) s 1.M 2E-1023
NUMBER REPRESENTATION
Floating Point Representation (Double Precision)
ve under flow + ve under flow
ve over flow + ve over flow
(2252) 21023 1.0 2-1022 1.0 2 1022 (2252) 21023
IEEE 754 Double Precision Special Number Representation
E(Exponent) M(Mantissa) Number Represented
2047 0 NaN (Not a number)
2047 0 Infinite Number
1 to 2046 Any Value FP Number
0 0 X=(1)s2-126 (0.m)
(Denormalized Form)
0 0 Represents + 0 and 0
E.g., Nan : sqrt (1),
1.0/0.0=1.0/0.0=+, 1.0/0.0=
P2. Represent +20 in IEEE754 Single Precision format
P3. Find the decimal value of the IEEE754 floating-point number
40A00000H
Q. The format of the single-precision floating-point representation of a
real number as per the IEEE 754 standard is as follows:
Sign exponent mantissa
Which one of the following choices is correct with respect to the
smallest normalized positive number represented using the standard?
(a) Exponent = 00000000 and mantissa = 00000000000000000000000
(b) Exponent = 00000000 and mantissa = 00000000000000000000001
(c) Exponent = 00000001 and mantissa = 00000000000000000000000
(d) Exponent = 00000001 and mantissa = 00000000000000000000001
Floating Point
Arithmetic
Signed Multiplication
Booth’s Algorithm
Multiply
Booth’s Algorithm for multiplication of signed 2’s
Multiplicand in BR Multiplier in Q
AC O
Q -1 O
complement numbers
SC n
= 10 =01
Q0 Q-1
=00
or 11
Ashr (AC & Q) SCSC1
0 =0
SC
END
Q0Q -1 Q -1
Operation A Q
Q0Q -1 Q -1
Operation A Q
Booth’s Code
P. Find the Booth’s Code for Multiplicand -20 10
Memory Organization
Microcomputer
Address Bus
CPU
Register
ALU Array Memory I/O Devices
Timing and Data Bus
Control Unit
Control Bus
Microcomputer
Memory
CPU
I/O Devices
Microcomputer
Main Auxiliary
Memory Memory
CPU
I/O Devices
Microcomputer
Main Auxiliary
Memory Memory
CPU
I/O Devices
Microcomputer
Cache Main Auxiliary
Memory Memory Memory
CPU
I/O Devices
Smaller
Faster and
Costlier Registers
Cache
Larger
Slower and
Cheaper Main Memory
Magnetic Disk
Magnetic Tape
Smaller
Faster and
Costlier Registers
Cache
Larger
Slower and
Cheaper Main Memory
Magnetic Disk
Magnetic Tape
Two Level Memory Organization
1. Independent
2. Hierarchical
Two Level Memory Organization
1. Independent
L1
CPU
L2
Two Level Memory Organization
2. Hierarchical
CPU
L1
L2
Three Level Memory Organization
1. Independent
L1
CPU
L2
L3
Two Level Memory Organization
2. Hierarchical
CPU
L1
L2
L3
P) Consider a system with 2 level caches . Access times of
L1,L2 and Main memory are 1ns, 10ns and 500ns.Hit ratio
of L1 and L2 are 0.8 and 0.9. What is Average access time
of system ignoring search time with in cache.
a) 13.0 ns
b) 12.8 ns
c) 12.6 ns
d) 12.4 ns
P) Consider a system with 2 level caches . Access times of
L1,L2 and Main memory are 1ns, 10ns and 500ns.Hit ratio of
L1 and L2 are 0.8 and 0.9. What is Average access time of
system ignoring search time with in cache.
Solution: It indicates Independent 2 level organization
Tavg = H1.T1 + (1- H1).H2.T2 + (1- H1) (1- H2)T3
Q. Which of the following is/are false?
(a) Processor can directly access data from secondary memory.
(b) Primary memory are used as backup memory.
(c) Primary memory stores the active instructions and data for the
program being executed on the processor.
(d) Primary memory can store only instructions.
Q. Which of the following is/are false?
(a) Central Processing Unit (CPU) consists of Control Unit,
Arithmetic Logic Unit (ALU) and Primary Memory.
(b) There are broadly two types of memory, primary memory and
secondary memory.
(c) The arithmetic and logic operations are performed in the control
unit.
(d) Control Unit is a part of main memory.
Byte and word Addressable Memory
Byte Addressable and word Addressable Memory
Memory Size No. of the required to No. of bits required
address each WORD to address each
BYTE
A) 4096 * 16
B) 512 * 64
C) 1024 * 32
Microoperations
and
RTL
Memory
CPU
PC Reg Array
R0 MA
ALU
IR R1 R
R2
SP R3
CLK Control Unit R4 MDR
ACC
Register Transfer Language (RTL):
It is the symbolic representation of
Microoperation
Register Transfer Language (RTL)
a) MOV R1,R2 ……. R1 R2
b) ADD R0,R1 …….. R0 R0 + R1
INSTRUCTION FORMAT
Opcode Expanding
Problems
on
INSTRUCTION FORMAT
Q.In a computer the length of the Instruction is 10 bits and
it has 32 Registers. The computer supports Opcode
Expanding. If it has 20 one Address Instructions find the
number of zero Address Instructions.
Q.In an 11 bit computer Instruction format the address field
is 4 bits. The computer uses expanding opcode technique
and has 5 two address instructions and 32 one address
instructions. The number of zero address instructions it
can support is ________.
(a) 512
(b) 256
(c) 1024
(d) 2048
Topic : Instruction format
Q. Consider a processor with 36 registers and instruction set size is 20. Each
instruction has four fields, namely opcode, two register operands and one
immediate operand. Word size of the processor is 24 bit; The immediate operand
is expressed in signed 2's complement notation. The smallest integer that can be
represented in immediate field is ______.
Q.Tow registers are initialized as R1 = 30 and R2 = 25. The
instruction ADD R1, R2 is memory location 2018 H. If the
size of an instruction is 4 byte, then after the execution of
the instruction the value of PC, R1 and R2 will be.
(a) PC = 2018 H, R1 = 55, R2 = 25
(b) PC = 2018 H, R1 = 55, R2 = 00
(c) PC = 201CH, R1 = 55, R2 = 25
(d) PC = 201CH, R1 = 55, R2 = 25
Q.Consider a 32-bit machine whose as instruction (ADD R1,
R2) is stored at memory location 2041H. What will be the
value of IR and PC while the instruction is fetched and
executed? Consider the size of the instruction is 32-bit.
(a) IR = ADD R1, R2, PC = 2004H
(b) IR = 2004H, PC=ADD R1, R2
(c) IR = ADD R1, R2, PC = 2006H
(d) IR = 2008H, PC = ADD R1, R2
Q.Consider a 32-bit machine where an instruction (SUB R1,
LOCA) is stored at location 2004H. LOCA is a memory
location whose value is 1024H. The number of memory
access required to execute this instruction will be
_______ ?
Q.A digital computer has memory capacity of 32767 words
with 48 bits per word. The instruction code format
consists of 8 bits for the operation part and 16 bits for the
address part. Two instructions are packed in one memory
word and 48 bits instruction register IR is available in the
control unit. Formulate the procedure for fetching and
executing the instructions for this computer.
(IES-EC-19) (20 M)
Q.A digital computer has a memory unit with 28 bits per
word. The instruction set consists of 235 different
operations. All instruction have an operation code part
(op code) and an address part. Each instruction is stored
in one word memory.
(i) How many bits are reserved for operation code?
[IES-EC-21][5M]
(ii) How many bits are left for the address part of the
instruction?
[IES-EC-21][5M]
(iii) What is the maximum size for the memory?
[IES-EC-21][5M]
Q.A digital computer has a memory unit with 32 bits per
word. The instruction set consists of 240 different
operations. All instructions have an operation code part
(opcode) and an address part (allowed for only one
address). Each instruction is stored in one word of
memory
(i) How many bits are needed for the opcode?
(ii) How many bits are left for the address part of the
instruction?
(iii) What is the maximum allowable size of the memory?
(IES-EC-19) (10 M)
Q.A system has 16 bits instruction that support zero
address, one address and two address instructions.
Assume each address field size is 5 bits, it is designed for
supporting '40' number of two address instructions, '400'
number of one address instructions. The maximum
number of zero address instructions that can be
formulated is ______.
ADDRESSING MODES
Q. After executing the instruction ADD R1, R1, 4(R2),
find R1 value
Given R1 = 67 R2 = 100
Address 96 100 104 108
Value 0 10 35 -17
Q. Registers R1 and R2 contain values 300 and 1200 respectively in
decimal, and the word length of the processor is 32 bits. The
effective address of the memory operand in decimal for the
instruction “STORE R5, 70 (R1, R2)” will be ________.
Q. Find EA and value of AC for the following addressing
modes
1. Direct Addressing
2. Indirect Addressing
3. Immediate Addressing
4. Register Addressing
5. Reg Indirect
6. Relative Addressing
7. Index Addressing
8. Base Register Addressing
9. Auto Increment Addressing
Address Load Ac Mode
201 Address =
500 Instructio
202 Next n
instruction
399 450
400 700
500 800
600 900
702 325
800 300
900PC = 200580
Given R1 = 400 XR
= 100
Address Load to AC Mode Find EA and value of AC for the following
201 Address=500 Addressing modes
202 Next Instruction
1. Direct Addressing
399 450 2. Indirect Addressing
400 700 3. Immediate Addressing
500 800
4. Register Addressing
600 900
5. Reg Indirect
702 325 6. Relative Indirect
800 300 7. Index Addressing
900 580
8. Base Register Addressing
Given 9. 8. Auto Increment Addressing
PC=200 R1=400 XR=100 10. Auto Decrementing Addressing
Q. Consider a RISC machine where each instruction is
exactly 4 bytes long. conditional and unconditional
branch instruction use PC relative addressing mode
with offset specified in bytes to the target location of
the branch instruction. Further the offset is always
with respect to the address of the next instruction in
Instprogram
the Instruction
sequence
No
i: Add R2, R3, R4
i +1: Sub R5, R6,R7
i+2: cmp R1,R9,R10
i+3: beq R1, offset
If the target of the branch instruction is i, then the
decimal value of the offset is _______
(a) -10
(b) -16
(c) -22
(d) -25
Q. The memory location 1000, 1001 and 1020 have
data values 18, 1 and 16 respectively before
executing the following program.
MOVI Rs, 1 ;Move immediate
LOAD Rd, 1000(Rs)
ADDI Rd, 1000
STOREI 0(Rd), 20 ;store immediate
Which of the statements below is true after the
above program is executed
(a) Memory location 1000 has a value 20
(b) Memory location 1020 has a value 20
(c) Memory location 1021 has a value 20
(d) Memory location 1001 has a value 20
INSTRUCTION FORMAT
Q.Consider the following instruction
2500: ADD @ R6, R1
Where 2500 is the memory address of the instruction,
ADD is the operation @ R6 represents Register Indirect
Addressing mode content of R is '500', content of R1 is
'400' and memory address content of 500 is 150 and 400
address content is 250. During the execution of the above
instruction, the input operands are added and result is
placed at the memory address given by R6. (All values are
given in decimal and R1, R6 are processing registers).
Q. Consider a three word machine instruction
ADD A[R0], @ B
The first operand uses indexed addressing mode with
R0 as the index register. The second operand uses
indirect addressing mode. A and B memory
addresses residing at the second and third words
respectively. The first word of the instruction
specifies the opcode. Find the number of memory
cycles required to execute the instruction is ______
(a) 3
(b) 4
(c) 6
INSTRUCTION SET ARCHITECTURE
Q.Match the pair in the following questions
List I List II
A. Base addressing P. Reentranecy
B. Indexed Q. Accumulator
addressing R. Array
C. Stack addressing S. Position Independent
D. Implied addressing
Codes:
(a) A – S; B – R; C – P; D – Q
(b) A – S; B – R; C – Q; D – P
(c) A – R; B – S; C – Q; D – P
(d) A – R; B – S; C – P; D – Q
CPU Performance
Problems on
CPU Performance
Topic : CPU
Q. Suppose a program requires 1000 instructions to execute. The
average number of cycles per instruction (CPI) is 1.5. The clock
frequency of the machine is 2.0 GHz. Time required to execute the
program will be _________ nanoseconds.
Topic : CPU
Q. Consider a program with 50 million instructions, a machine requires
25 milliseconds to execute this program. What will be the MIPS
rating of the machine?
(a) 20
(b) 200
(c) 2000
(d) 20000
Q.A Program is running on a machine with the following
parameters.
Find the execution time
Total number of instructions executed = 50,000,000
Average CPI for the program = 2.7
CPU Clock Rate = 2.0 GHz
Topic : CPU
Q. Find CPIavg and MIPS if clock rate is 19.6 GHz.
S.No Types of CPI Count Total no of
Instrucitons cycles
1 Load/Store 5 40
2 ALU 4 20
3 Branching 6 10
4 Other 5 30
Topic : CPU Performance
Q. In a processor with CISC Architecture, the load, store
Branch and ALU instructions frequency are 30%,
20%, 40% and 10% respectively and CPI values of 3,
2.5, 1 and 4 respectively.
Find the overall CPI?
Topic : CPU
Q. Which of the following is/are false?
(a) Central Processing Unit (CPU) consists of Control Unit,
Arithmetic Logic Unit (ALU) and Primary Memory.
(b) There are broadly two types of memory, primary memory and
secondary memory.
(c) The arithmetic and logic operations are performed in the control
unit.
(d) Control Unit is a part of main memory.
Topic : CPU Performance
Q.A Machine A executes a program with an average CPI of
2.3. An other Machine B (with same ISA and better
Compiler) that executes the same program with 20% less
instructions and with a CPI of 1.7 at 1.2 GHz.
What should be the clock rate of A so that the two
machines have the same performance?
Q.A program is running on a Machine with IC = 50,000,000,
Average CPI = 2.7 and Clock rate = 2.0 GHz. If the same
program is executed using a new compiler with IC =
40,000,000, Average CPI = 3.0 and Clock rate = 2.4
GHz. Find the Speed up factor.
Speedup = Etold/ETnew
P)
Program A on P1 (CT=1 st) Program A on P1 (CT=0.714 ns)
IC=10000 IC=12000
Fraction Br: L/S ALU = 20 : 40 : 40 Fraction Br : L/S : ALU = 25 : 50 : 25
CPI Br : L/S : ALU = 5 : 2 : 15 CPI Br : L/S : ALU = 5 : 3 : 1.5
P)
Pgm A on P1 (CT=1 st) Pgm A on P1 (CT=0.714 ns)
IC=10000 IC=12000
Fraction Br: L/S ALU = 20 : 40 : Fraction Br : L/S : ALU = 25 :
40 50 : 25
CPI Br : L/S : ALU = 5 : 2 : 15 CPI Br : L/S : ALU = 5 : 3 : 1.5
a) CPIA_P1= (0.2*5+0.4*2+0.4*1.5)=2.4
Execution Time = 2.4 10000 1 ns = 24000ns
b) CPIB_P2= (0.25*5+0.5*3+0.25*1.5)=3.125
Execution Time = 3.125 12000 0.714 ns = 26775ns
Q. Suppose that a machine X executes a program with an average CPI
of 2.5. Consider another machine Y (with same instruction set and a
little better compiler) that executes the same program with 10% less
instructions and with the CPI of 1.5 at 4GHz. What should be the
clock frequency of X so that both the machines have same
performance?
a. 7.40GHz
b. 7.40MHz
c. 7.40KHz
d. 7.40Hz
Q.Consider a 32-bit machine where an instruction (SUB R1,
LOCA) is stored at location 2004H. LOCA is a memory
location whose value is 1024H. The number of memory
access required to execute this instruction will be
_______ ?
P) In a computer the length of the instruction is 8 bits and it has 8
Registers. The Computer supports Opcode Expanding. If it has 3 Two
Address Instructions and 2 One Address Instructions. Find the
number of zero Address Instructions.
Q.In a computer the length of the Instruction is 10 bits and
it has 32 Registers. The computer supports Opcode
Expanding. If it has 20 one Address Instructions find the
number of zero Address Instructions.
Q.A system has 16 bits instruction that support zero
address, one address and two address instructions.
Assume each address field size is 5 bits, it is designed for
supporting '40' number of two address instructions, '400'
number of one address instructions. The maximum
number of zero address instructions that can be
formulated is ______.
Q.In an 11 bit computer Instruction format the address field
is 4 bits. The computer uses expanding opcode technique
and has 5 two address instructions and 32 one address
instructions. The number of zero address instructions it
can support is ________.
(a) 512
(b) 256
(c) 1024
(d) 2048
Q. The memory location 1000, 1001 and 1020 have
data values 18, 1 and 16 respectively before
executing the following program.
MOVI Rs, 1 ;Move immediate
LOAD Rd, 1000(Rs)
ADDI Rd, 1000
STOREI 0(Rd), 20 ;store immediate
Which of the statements below is true after the
above program is executed
(a) Memory location 1000 has a value 20
(b) Memory location 1020 has a value 20
(c) Memory location 1021 has a value 20
(d) Memory location 1001 has a value 20
Q. After executing the instruction ADD R1, R1, 4(R2),
find R1 value
Given R1 = 67 R2 = 100
Address 96 100 104 108
Value 0 10 35 -17
Instruction Cycle
Instruction: ADD R1, R2
Microcomputer Block Diagram
