COA - General Register Organization

The CPU is the brain of the computer, and it is responsible for executing instructions and performing calculations. If CPU constantly uses main memory to store read and write intermediate data, the overall calculation will be very slow. So to speed up the processing, the CPU has a small amount of high-speed memory called registers. The modern CPUs are equipped with multiple internal, high-speed storage locations called General Purpose Registers.

Need for General Purpose Registers

We have discussed that an accumulator-based organization has only one register (the AC) for performing all operations. This means that every time we want to perform an operation, we need to load the operands into the AC, perform the operation, and then store the result back to memory if needed. This can lead to a lot of memory access and can slow down the execution of programs.

In a General Register Organization, the CPU contains a set of registers (e.g., R1, R2, R3 .... ) that can be used interchangeably for various functions.

• They can hold data, memory addresses, or intermediate results.
• Programmers can use them as pointers, counters, or temporary storage.
• Having data immediately available inside the CPU drastically reduces memory access times and speeds up program execution.

In a general register organization, the instruction set is designed to allow operations to be performed directly on the registers. This means that instructions can specify which registers to use for the operands and where to store the results. This allows for more efficient use of the CPU's resources and can lead to faster execution of programs.

General Organization of Registers

In a general register organization, the CPU typically has a set of registers that are used for various purposes. When a CPU has multiple general registers, they must be connected to the Arithmetic Logic Unit (ALU) in a way that allows any register to be used as an input and any register to be used as the destination for the output. This is achieved using a complex internal bus system composed of Multiplexers (MUX) and a Decoder. The image below shows a block diagram of a general register organization with 7 registers (R0 to R6) connected to two 7-to-1 multiplexers (MUX) and a 3-to-8 decoder.

How this Architecture Works?

In this architecture, system is designed to perform operations on data stored in registers and write the result back.

• Register File (Registers 0-6): These seven blocks are where data is stored. Each one can hold a value (e.g., a 16-bit number). We can think of them as small, fast storage locations that the CPU can access quickly.
• Multiplexers (MUX A & MUX B): These are data selectors. Each MUX has inputs from all 7 registers. We provide a control signal (a select code) to each MUX to choose one of the registers. MUX A connects the value from your chosen "A" register to the first ALU input. MUX B connects the value from your chosen "B" register to the second ALU input.
• Arithmetic Logic Unit (ALU): The ALU is the "calculator" of the system. It takes two inputs (from MUX A and MUX B) and performs an operation like ADD, SUB (subtract), AND, or OR as determined by a control signal.
• Data Bus: The output from the ALU carries the computed result. This is a common data line that connects to the input of all 7 registers.
• 3-to-8 Decoder: This component determines where the ALU result gets written. A 3-bit input address (values 0-7) is decoded into 8 separate output lines, only one of which will be active at any given time.