Quasi-Resonant Controllers with Integrated Power MOSFET

STR-Y6700 Series

General Descriptions Package

The STR-Y6700 series are power ICs for switching TO220F-7L
power supplies, incorporating a MOSFET and a
quasi-resonant controller IC.
Including an auto standby function in the controller,
the product achieves the low standby power by the
automatic switching between the PWM operation in
normal operation, one bottom-skip operation under
medium to light load conditions and the burst-oscillation
under light load conditions.
Not to Scale
The product achieves high cost-performance power
supply systems with few external components.
Features Lineup
• Multi-mode Control • Electrical Characteristics
The optimum operation depending on load conditions Products VDSS(min.) RDS(ON)(max.)
is changed automatically and is achieved high STR–Y6735
efficiency operation across the full range of loads. 500 V 0.8 Ω
STR–Y6735A
STR–Y6753 1.9 Ω
Operation Mode 650 V
STR–Y6754 1.4 Ω
Normal load ------------------------- Quasi-resonant mode
STR–Y6766
Medium to light load -------------One bottom-skip mode 1.7 Ω
STR–Y6766A
Light load -------------------------- Burst oscillation mode
(Auto standby function) STR–Y6765 800 V 2.2 Ω
• No load power consumption STR–Y6763
3.5 Ω
STR–Y6763A
PIN < 30 mW (100VAC)
PIN < 50 mW (230VAC)
• Leading Edge Blanking Function
• Output Power, POUT(2)
POUT (Open frame)
• Bias Assist Function Products
• Built-in startup circuit reduces 380VDC 85~265VAC
• Protections STR–Y6735
120 W(100VAC) –
STR–Y6735A
Overcurrent Protection 1 (OCP1): Pulse-by-Pulse, with
Input Compensation Function STR–Y6753 100 W 60 W
Overcurrent Protection 2 (OCP2)(1): Latched shutdown STR–Y6754 120 W 67 W
Overload Protection (OLP): Latched shutdown STR–Y6766
140 W 80 W
Overvoltage Protection (OVP): Latched shutdown STR–Y6766A
Thermal Shutdown Protection (TSD): Latched shutdown STR–Y6765 120 W 70 W
(1)
Products with the last letter "A" don’t have the STR–Y6763
80 W 50 W
STR–Y6763A
OCP2 function.
(2)
The output power is actual continues power that is measured at
50 °C ambient. The peak output power can be 120 to 140 % of
Typical Application the value stated here. Core size, ON Duty, and thermal design
affect the output power. It may be less than the value stated here.
L51
BR1 T1 D51 VOUT(+)
VAC
P
C1 R54
PC1 R51

C51
R55 Applications
• White goods
S R52 C53
U1

• Office automation equipment

C52 R53

D2 R2 U51
STR-Y6700
• Industrial equipment
R56

C3
FB/OLP

D
VOUT(-)
S/OCP
D/ST

GND
VCC

BD
NF
2

DZBD
1 2 3 4 5 6 7

RBD1

R3
RBD2
ROCP CBD
C4 C5 PC1
CY

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STR-Y6700 Series

CONTENTS
General Descriptions ------------------------------------------------------------------------------------------ 1
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 3
2. Electrical Characteristics -------------------------------------------------------------------------------- 4
3. Performance Curves -------------------------------------------------------------------------------------- 6
3.1 Derating Curves ------------------------------------------------------------------------------------ 6
3.2 Ambient Temperature versus Power Dissipation Curves ---------------------------------- 6
3.3 MOSFET Safe Operating Area Curves ------------------------------------------------------- 8
3.4 Transient Thermal Resistance Curves --------------------------------------------------------- 9
4. Block Diagram ------------------------------------------------------------------------------------------- 10
5. Pin Configuration Definitions------------------------------------------------------------------------- 10
6. Typical Application ------------------------------------------------------------------------------------- 11
7. Physical Dimensions ------------------------------------------------------------------------------------ 12
8. Marking Diagram --------------------------------------------------------------------------------------- 12
9. Operational Description ------------------------------------------------------------------------------- 13
9.1 Startup Operation ------------------------------------------------------------------------------- 13
9.2 Undervoltage Lockout (UVLO) --------------------------------------------------------------- 13
9.3 Bias Assist Function ----------------------------------------------------------------------------- 13
9.4 Soft Start Function ------------------------------------------------------------------------------ 14
9.5 Constant Output Voltage Control ------------------------------------------------------------ 15
9.6 Leading Edge Blanking Function ------------------------------------------------------------- 15
9.7 Quasi-Resonant Operation and Bottom-On Timing Setup ------------------------------ 15
9.7.1 Quasi-Resonant Operation ------------------------------------------------------------ 15
9.7.2 Bottom-On Timing Setup ------------------------------------------------------------- 16
9.8 BD Pin Blanking Time -------------------------------------------------------------------------- 17
9.9 Multi-mode Control ----------------------------------------------------------------------------- 18
9.9.1 One Bottom-Skip Quasi-Resonant Operation ------------------------------------- 18
9.9.2 Automatic Standby Mode Function ------------------------------------------------- 19
9.10 Maximum On-Time Limitation Function --------------------------------------------------- 19
9.11 Overcurrent Protection (OCP) ---------------------------------------------------------------- 20
9.11.1 Overcurrent Protection 1 (OCP1) --------------------------------------------------- 20
9.11.2 Overcurrent Protection 2 (OCP2) --------------------------------------------------- 20
9.11.3 OCP1 Input Compensation Function ----------------------------------------------- 20
9.11.4 When Overcurrent Input Compensation is Not Required ---------------------- 23
9.12 Overload Protection (OLP) -------------------------------------------------------------------- 23
9.13 Overvoltage Protection (OVP) ---------------------------------------------------------------- 24
9.14 Thermal Shutdown (TSD)---------------------------------------------------------------------- 24
10. Design Notes ---------------------------------------------------------------------------------------------- 25
10.1 External Components --------------------------------------------------------------------------- 25
10.2 Transformer Design ----------------------------------------------------------------------------- 27
10.3 PCB Trace Layout and Component Placement -------------------------------------------- 28
11. Pattern Layout Example ------------------------------------------------------------------------------- 30
12. Reference Design of Power Supply ------------------------------------------------------------------ 31
IMPORTANT NOTES ------------------------------------------------------------------------------------- 33

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1. Absolute Maximum Ratings

• Current polarities are defined as follows: a current flow going into the IC (sinking) is positive current (+); and a
current flow coming out of the IC (sourcing) is negative current (−).
• Unless otherwise specified TA = 25 °C
Parameter Symbol Test Conditions Pins Rating Units Notes
6.7 STR–Y6763 / 63A
8.9 STR–Y6765
9.2 STR–Y6753
Drain Peak Current(1) IDPEAK Single pulse 1–2 A
10.5 STR–Y6766 / 66A
11.0 STR–Y6754
14.6 STR–Y6735 / 35A
6.7 STR–Y6763 / 63A
8.9 STR–Y6765
Single pulse 9.2 STR–Y6753
Maximum Switching Current(2) IDMAX 1–2 A
Ta= −20 to 125°C 10.5 STR–Y6766 / 66A
11.0 STR–Y6754
14.6 STR–Y6735 / 35A
ILPEAK=2.3A 60 STR–Y6763 / 63A
ILPEAK=2.6A 77 STR–Y6765
ILPEAK=2.9A 99 STR–Y6753
Avalanche Energy(3)(4) EAS 1–2 mJ
ILPEAK=3.2A 116 STR–Y6766 / 66A
ILPEAK=4.1A 198 STR–Y6754
ILPEAK=3.5A 152 STR–Y6735 / 35A
D/ST Pin Voltage VSTARTUP 1−4 − 1.0 to VDSS V
S/OCP Pin Voltage VOCP 2–4 − 2.0 to 6.0 V
VCC Pin Voltage VCC 3–4 35 V
FB/OLP Pin Voltage VFB 5–4 − 0.3 to 7.0 V
FB/OLP Pin Sink Current IFB 5–4 10.0 mA
BD Pin Voltage VBD 6–4 − 6.0 to 6.0 V
19.9 STR–Y6763 / 63A
21.8 STR–Y6765
With infinite 20.2 STR–Y6753
1–2 W
Power Dissipation( 5) PD1 heatsink
23.6 STR–Y6766 / 66A
STR–Y6735 / 35A
21.5 STR–Y6754
Without heatsink 1–2 1.8 W
Control Part Power Dissipation PD2 VCC×ICC 3–4 0.8 W
Internal Frame Temperature in
TF − − 20 to 115 °C
Operation
Operating Ambient Temperature TOP − − 20 to 115 °C
Storage Temperature Tstg − − 40 to 125 °C
Junction Temperature Tch − 150 °C

(1)
Refer to 3.3 MOSFET Safe Operating Area Curves
(2)
The maximum switching current is the drain current determined by the drive voltage of the IC and threshold voltage
(Vth) of the MOSFET.
(3)
Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve
(4)
Single pulse, VDD = 99 V, L = 20 mH
(5)
Refer to 3.2 TA-PD1curves.

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2. Electrical Characteristics
• The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
• Unless otherwise specified, TA = 25 °C, VCC = 20 V
Test
Parameter Symbol Pins Min. Typ. Max. Units Notes
Conditions
Power Supply Startup Operation
Operation Start Voltage VCC(ON) 3−4 13.8 15.1 17.3 V
Operation Stop Voltage (1)
VCC(OFF) 3−4 8.4 9.4 10.7 V
Circuit Current in Operation ICC(ON) 3−4 − 1.3 3.7 mA
Circuit Current in
ICC(OFF) VCC = 13 V 3−4 − 4.5 50 µA
Non-Operation
Startup Circuit Operation
VSTART(ON) 1−4 42 57 72 V
Voltage
Startup Current ICC(STARTUP) VCC = 13 V 3−4 − 4.5 − 3.1 − 1.0 mA
Startup Current Biasing
VCC(BIAS) 3−4 9.5 11.0 12.5 V
Threshold Voltage
PWM Switching Frequency fOSC 1−4 18.4 21.0 24.4 kHz
Soft Start Operation Duration tSS 1−4 − 6.05 − ms
Normal Operation
Bottom-Skip Operation
VOCP(BS1) 2−4 0.487 0.572 0.665 V
Threshold Voltage 1
Bottom-Skip Operation
VOCP(BS2) 2−4 0.200 0.289 0.380 V
Threshold Voltage 2
Quasi-Resonant Operation
VBD(TH1) 6−4 0.14 0.24 0.34 V
Threshold Voltage 1
Quasi-Resonant Operation
VBD(TH2) 6−4 0.07 0.17 0.27 V
Threshold Voltage 2(2)
Maximum Feedback Current IFB(MAX) 5−4 −320 −205 −120 µA
Standby Operation
Standby Operation Threshold
VFB(STBOP) 5−4 0.45 0.80 1.15 V
Voltage
Protected Operation
Maximum On-Time tON(MAX) 1−4 30.0 40.0 50.0 µs
STR–Y6735
− 455 − / 35A/ 65/
Leading Edge Blanking Time tON(LEB) 1−4 ns 66/ 54
STR–Y6763
− 470 − / 63A/ 53
Overcurrent Detection 1
Threshold Voltage in Input VOCP(L) VBD = –3V 2−4 0.560 0.660 0.760 V
Compensation Operation
Overcurrent Detection 1
Threshold Voltage in Normal VOCP(H) VBD = 0V 2−4 0.820 0.910 1.000 V
Operation
Products
Overcurrent Detection 2 without the
VOCP(La.OFF) 2−4 1.65 1.83 2.01 V
Threshold Voltage last letter
"A"
(1)
VCC(OFF) < VCC(BIAS) always.
(2)
VBD(TH2) < VBD(TH1) always.

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Test
Parameter Symbol Pins Min. Typ. Max. Units Notes
Conditions
BD Pin Source Current IBD(O) 6−4 − 250 − 83 − 30 µA
OLP Bias Current IFB(OLP) 5−4 − 15 − 10 −5 µA
OLP Threshold Voltage VFB(OLP) 5−4 5.50 5.96 6.40 V
FB Pin Maximum Voltage in
VFB(MAX) 5−4 3.70 4.05 4.40 V
Feedback Operation
OVP Threshold Voltage VCC(OVP) 3− 4 28.5 31.5 34.0 V
Thermal Shutdown Operating
Tj(TSD) − 135 − − °C
Temperature
MOSFET
STR-Y6735 /
500 − − 35A
STR-Y6753 /
Drain-to-Source Breakdown
IDS=300μA
650 − −
VDSS 1–2 V 54
Voltage
STR-Y6763 /
800 − − 63A / 65 /66
/66A
Drain Leakage Current IDSS VDS=VDSS 1–2 − − 300 μA
STR-Y6735
− − 0.8 / 35A
− − 1.4 STR–Y6754
STR–Y6766
1.7 / 66A
On Resistance RDS(ON) 1–2 Ω
1.9 STR–Y6753

2.2 STR–Y6765
STR–Y6763
− − 3.5 / 63A
STR–Y6753
− − 250 ns / 63 / 63A
Switching Time tf 1–2 STR-Y6735
− − 300 ns / 35A / 54 /
66 / 66A / 65
Thermal Resistance
STR-Y6735
− 2.4 2.7 / 35A / 54
STR–Y6766
− 1.9 2.2 / 66A
Channel to Frame Thermal
θch-F − − 2.7 3.1 °C/W STR–Y6753
Resistance( 3)
− 2.3 2.6 STR–Y6765
STR–Y6763
− 2.8 3.2 / 63A
STR-Y6735
− 5.1 5.9 / 35A / 54
STR–Y6766
− 4.6 5.3 / 66A
Channel to Case Thermal
θch-C − − 5.4 6.2 °C/W STR–Y6753
Resistance( 4)
− 5.0 5.8 STR–Y6765
STR–Y6763
− 5.5 6.3 / 63A

(3)
θch-F is thermal resistance between channel and internal frame.
(4)
θch-C is thermal resistance between channel and case. Case temperature is measured at the backside surface.

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3. Performance Curves

3.1 Derating Curves

100 100

EAS Temperature Derating Coefficient (%)

Temperature Derating Coefficient (%)

80 80
Safe Operating Area

60 60

40 40

20
20

0
0
115 25 50 75 100 125 150
0 25 50 75 100 125

Internal frame temperature, TF (°C) Channel Temperature, Tch (°C)

Figure 3-2 Avalanche Energy Derating Coefficient

Figure 3-1 SOA Temperature Derating Coefficient Curve
Curve

3.2 Ambient Temperature versus Power Dissipation Curves

• STR–Y6735、STR–Y6735A • STR–Y6753

30 30

25 25
Power Dissipation, PD1 (W)

Power Dissipation, PD1 (W)

21.5 With infinite heatsink

20.2
20 20
With infinite heatsink

15 15

10 10

Without heatsink Without heatsink

5 5
1.8 1.8

0 0
115
0 25 50 75 100 115 125 150 0 25 50 75 100 125 150
Ambient Temperature, TA (°C ) Ambient Temperature, TA (°C )

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• STR–Y6754 • STR–Y6763、STR–Y6763A
30 30

25 25
21.5

Power Dissipation, PD1 (W)

Power Dissipation, PD1 (W)

With infinite heatsink 19.9

20 20
With infinite heatsink

15 15

10 10
Without heatsink
Without heatsink
5 5
1.8 1.8

0 0
115
0 25 50 75 100 125 150 0 25 50 75 100 115 125 150
Ambient Temperature, TA (°C ) Ambient Temperature, TA (°C )
• STR–Y6765 • STR–Y6766、STR–Y6766A
30 30
23.6
25 25
21.8
Power Dissipation, PD1 (W)
Power Dissipation, PD1 (W)

With infinite heatsink

20 With infinite heatsink 20

15 15

10 10

Without heatsink Without heatsink

5 5
1.8 1.8

0 0
0 25 50 75 100 115 125 150 0 25 50 75 100 115 125 150

Ambient Temperature, TA (°C ) Ambient Temperature, TA (°C )

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3.3 MOSFET Safe Operating Area Curves

• When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1.
• The broken line in the safe operating area curve is the drain current curve limited by on-resistance.
• Unless otherwise specified, TA = 25 °C, Single pulse
• STR–Y6735, STR–Y6735A • STR–Y6753
100
100

0.1ms
0.1ms 10
Drain Current, ID (A)

Drain Current, ID (A)

10

1 1ms
1ms
1
0.1

0.1 0.01
10 100 1000 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

• STR–Y6754 • STR–Y6763, STR–Y6763A

100 10
0.1ms
Drain Current, ID (A)

0.1ms
Drain Current, ID (A)

10 1
1ms

1ms
1 0.1

0.1 0.01
10 100 1000 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

• STR–Y6765 • STR–Y6766, STR–Y6766A

10 100
0.1ms

0.1ms
Drain Current, ID (A)

1ms
1 10
Drain Current, ID (A)

1ms
0.1 1

0.01 0.1
10 100 1000 10 100 1000
Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

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STR-Y6700 Series

3.4 Transient Thermal Resistance Curves

• STR–Y6735, STR–Y6735A, STR–Y6754, STR–Y6765
10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01

0.001
1µ 10µ 100µ 1m 10m 100m
Time (s)

• STR–Y6753, STR–Y6763, STR–Y6763A

10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01

0.001
1µ 10µ 100µ 1m 10m 100m
Time (s)

• STR–Y6766, STR–Y6766A
10
Transient Thermal Resistance

1
θch-c (°C/W)

0.1

0.01

0.001
1µ 10µ 100µ 1m 10m 100m
Time (s)

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STR-Y6700 Series

4. Block Diagram

VCC D/ST
3 STARTUP 1

UVLO
DRV
Reg / ICONST

S/OCP
OCP/BS 2
LATCH
LOGIC

NF FB/STB FB/OLP
7 OLP 5

OSC
GND BD
4 BD 6

BD_STR-Y6700_R1

5. Pin Configuration Definitions

Pin Name Descriptions
1 D/ST
1 D/ST MOSFET drain and startup current input
2 S/OCP MOSFET source and overcurrent protection
2 S/OCP
(OCP) signal input
3 VCC
Power supply voltage input for control part and
4 GND 3 VCC
overvoltage protection (OVP) signal input
5 FB/OLP
4 GND Ground
6 BD
7 NF Constant voltage control signal input and over
5 FB/OLP
load protection (OLP) signal input
(LF3051) Bottom Detection signal input, Input
6 BD
Compensation detection signal input
7 NF* (Non-function)

*For stable operation, NF pin should be connected to GND pin, using the shortest possible path.

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6. Typical Application
• The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation.
• In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the
D/ST pin and the S/OCP pin.
• For stable operation, NF pin should be connected to GND pin, using the shortest possible path.

CRD clamp snubber L51

BR1 T1 D51 VOUT(+)
VAC
C1 C2 R1 P R54
PC1 R51
D1
R55
C51
S R52 C53
U1
C52 R53

D2 R2 U51
STR-Y6700 R56

C3
FB/OLP

D
VOUT(-)
S/OCP
D/ST

GND
VCC

BD
NF
2

DZBD
1 2 3 4 5 6 7
CV RBD1

C(RC)
Damper snubber R3
RBD2
ROCP CBD
C4 C5 PC1
CY

Figure 6-1 Typical application

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STR-Y6700 Series

7. Physical Dimensions
• TO220F-7L

2.8 +0.2
10 ±0.2
4.2 ±0.2
Gate burr
2.6±0.2

（5.6）

3.2±0.2
15 ±0.3
（1.1）

2.6 ±0.1
（Measured at pin base）

5±0.5

5±0.5
10.4 ±0.5

7-0.62±0.15

R-end R-end
7-0.55 +0.2
-0.1

+0.2
5×P1.17±0.15 0.45 -0.1 2.54±0.6
2±0.15 ＝5.85±0.15
（Measured at pin base） （Measured at pin tip）
（Measured at pin base）

5.08±0.6
（Measured at pin tip）

0.5 0.5 0.5 0.5

Front view Side view

1 2 3 4 5 6 7

NOTES :
1) Dimension is in millimeters.
2) Leadform: LF No.3051
3) Gate burr indicates protrusion of 0.3 mm (max.).
4) Pin treatment Pb-free. Device composition compliant with the RoHS directive.

8. Marking Diagram

STR
Y67×××
Part Number
YMDDX
Lot Number:
2

1 2 7 Y is the last digit of the year of manufacture (0 to 9)

M is the month of the year (1 to 9, O, N or D)
DD is the day of the month (01 to 31)
X is the control number

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9. Operational Description winding so that VCC pin voltage becomes Equation (1)
within the specification of input and output voltage
• All of the parameter values used in these descriptions variation of power supply.
are typical values, unless they are specified as
minimum or maximum. VCC ( BIAS) (max .) < VCC < VCC ( OVP ) (min .)
• With regard to current direction, "+" indicates sink
current (toward the IC) and "–" indicates source
current (from the IC). ⇒12.5 (V) < VCC < 28.5 (V) (1)

The startup time of IC is determined by C3 capacitor

9.1 Startup Operation value. The approximate startup time tSTART (shown in
Figure 9-2) is calculated as follows:
Figure 9-1 shows the circuit around IC. Figure 9-2
shows the start up operation. VCC ( ON )－VCC ( INT )
t START = C3 × (2)
I CC (STRATUP )
BR1 T1
VAC
where,
C1 P tSTART : Startup time of IC (s)
VCC(INT) : Initial voltage on VCC pin (V)
1
U1 D/ST D2 R2
3
VCC 9.2 Undervoltage Lockout (UVLO)
C3 VD D Figure 9-3 shows the relationship of VCC pin voltage
4 and circuit current ICC. When VCC pin voltage decreases
GND
to VCC(OFF) = 9.4 V, the control circuit stops operation by
Undervoltage Lockout (UVLO) circuit, and reverts to
the state before startup.
Figure 9-1 VCC pin peripheral circuit
Circuit current, ICC
VCC pin
voltage
VCC(ON)
Stop Start

tSTART
Drain current,
ID
VCC（OFF） VCC（ON） VCC pin
voltage

Figure 9-2 Startup operation

Figure 9-3 Relationship between
VCC pin voltage and ICC
The IC incorporates the startup circuit. The circuit is
connected to D/ST pin. When D/ST pin voltage reaches
to Startup Circuit Operation Voltage VSTART(ON) = 57 V, 9.3 Bias Assist Function
the startup circuit starts operation.
During the startup process, the constant current, By the Bias Assist Function, the startup failure is
ICC(STARTUP) = − 3.1 mA, charges C3 at VCC pin. When prevented and the latched state is kept.
VCC pin voltage increases to VCC(ON) = 15.1 V, the The Bias Assist function is activated, when the VCC
control circuit starts operation. During the IC operation, voltage decreases to the Startup Current Biasing
the voltage rectified the auxiliary winding voltage, VD, Threshold Voltage, VCC(BIAS) = 11.0 V, in either of
of Figure 9-1 becomes a power source to the VCC pin. following condition:
After switching operation begins, the startup circuit the FB pin voltage is the Standby Operation Threshold
turns off automatically so that its current consumption Voltage, VFB(STBOP) = 0.80 V or less
becomes zero. or the IC is in the latched state due to activating the
The approximate value of auxiliary winding voltage is protection function.
about 20 V, taking account of the winding turns of D

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When the Bias Assist Function is activated, the VCC step-wisely (4 steps). This function reduces the voltage
pin voltage is kept almost constant voltage, VCC(BIAS) by and the current stress of MOSFET and secondary side
providing the startup current, ISTARTUP, from the startup rectifier diode.
circuit. Thus, the VCC pin voltage is kept more than During the soft start operation period, the operation is
VCC(OFF). in PWM operation, at an internally set operation
Since the startup failure is prevented by the Bias frequency, fOSC = 21.0 kHz.
Assist Function, the value of C3 connected to VCC pin Until BD pin voltage becomes the following condition
can be small. Thus, the startup time and the response after the soft start time, the switching operation is PWM
time of the OVP become shorter. control of fOSC = 21.0 kHz.
When BD pin voltage, VBD, becomes the following
The operation of the Bias Assist Function in startup is condition, the IC starts quasi-resonant operation.
as follows. It is necessary to check and adjust the startup
process based on actual operation in the application, so
that poor starting conditions may be avoided. Quasi-resonant operation starting condition
 VBD ≥ VBD(TH1) = 0.24 V
Figure 9-4 shows VCC pin voltage behavior during  The effective pulse width of quasi-resonant signal
the startup period. is 1.0 μs or more (refer to Figure 9-12)
After VCC pin voltage increases to VCC(ON) = 15.1 V
at startup, the IC starts the operation. Then circuit After the soft start period, D/ST pin current, ID, is
current increases and VCC pin voltage decreases. At the limited by the overcurrent protection (OCP), until the
same time, the auxiliary winding voltage VD increases in output voltage increases to the target operating voltage.
proportion to output voltage. These are all balanced to This period is given as tLIM.
produce VCC pin voltage. When tLIM is longer than the OLP Delay Time, tOLP,
When VCC pin voltage is decrease to VCC(OFF) = 9.4 V the output power is limited by the OLP operation (OLP).
in startup operation, the IC stops switching operation Thus, the tOLP must be set longer than tLIM (refer to
and a startup failure occurs. Section 9.13).
When the output load is light at startup, the output
voltage may become more than the target voltage due to Startup of IC Startup of SMPS
the delay of feedback circuit. In this case, the FB pin Normal operation
VCC pin voltage
voltage is decreased by the feedback control. When the tSTART
VCC(ON)
FB pin voltage decreases to the Standby Operation
Threshold Voltage, VFB(STBOP) = 0.80 V, or less, the IC VCC(OFF)
stops switching operation and VCC pin voltage
decreases. When VCC pin voltage decreases to VCC(BIAS),
tSS tLIM Time
the Bias Assist function is activated and the startup
failure is prevented. D/ST pin
current, ID
VCC pin Startup success
voltage IC starts operation
Target operating Time
VCC(ON) voltage PWM operation Quasi-resonant operation
VCC(BIAS) Increase with rising of BD pin voltage
output voltage
VBD(TH1)
Bias assist period
VCC(OFF)
Enlarged Waveform Time
Startup failure
PWM operation Quasi-resonant operation
Time

Figure 9-4 VCC pin voltage during startup period

The effective pulse width is
1.0µs or more
9.4 Soft Start Function
Figure 9-5 shows the behavior of VCC pin voltage, Figure 9-5 VCC and ID and VBD behavior during startup
drain current and BD pin voltage during the startup
period.
The IC activates the soft start circuitry during the
startup period. Soft start is fixed to tSS = 6.05 ms. During
the soft start period, over current threshold is increased

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9.5 Constant Output Voltage Control 9.6 Leading Edge Blanking Function
The IC achieves the constant voltage control of the The IC uses the peak-current-mode control method
power supply output by using the current-mode control for the constant voltage control of output.
method, which enhances the response speed and In peak-current-mode control method, there is a case
provides the stable operation. that the power MOSFET turns off due to unexpected
The IC compares the voltage, VROCP, of a current response of FB comparator or overcurrent protection
detection resistor with the target voltage, VSC, by the circuit (OCP) to the steep surge current in turning on a
internal FB comparator, and controls the peak value of power MOSFET.
VROCP so that it gets close to VSC, as shown in Figure 9-6 In order to prevent this response to the surge voltage
and Figure 9-7. VSC is generated by the FB/OLP pin in turning-on the power MOSFET, the Leading Edge
voltage. Blanking, tON(LEB) is built-in. During tON(LEB), the OCP
threshold voltage becomes VOCP(La.OFF) = 1.83 V in order
• Light load conditions not to respond to the turn-on drain current surge (refer to
When load conditions become lighter, the output Section 9.12).
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the 9.7 Quasi-Resonant Operation and
FB/OLP pin voltage decreases. Thus, VSC decreases, Bottom-On Timing Setup
and the peak value of VROCP is controlled to be low,
and the peak drain current of ID decreases.
This control prevents the output voltage from 9.7.1 Quasi-Resonant Operation
increasing.
Using quasi-resonant operation, switching loss and
• Heavy load conditions switching noise are reduced and it is possible to obtain
When load conditions become greater, the IC converters with high efficiency and low noise. This IC
performs the inverse operation to that described above. performs quasi-resonant operation during one
Thus, VSC increases and the peak drain current of ID bottom-skip operation.
increases. Figure 9-8 shows the circuit of a flyback converter.
This control prevents the output voltage from The meaning of symbols in Figure 9-8 is shown in Table
decreasing. 9-1. A flyback converter is a system that transfers the
energy stored in the transformer to the secondary side
when the primary side power MOSFET is turned off.
U1 After the energy is completely transferred to the
S/OCP GND FB/OLP secondary, when the power MOSFET keeps turning off,
2 4 5
the VDS begins free oscillation based on the LP and CV.
The quasi-resonant operation is the bottom-on operation that
the power MOSFET turns-on at the bottom point of free
R3 C5 PC1 oscillation of VDS.
VROCP ROCP IFB Figure 9-9 shows an ideal VDS waveform during
C4 bottom-on operation.
The delay time, tONDLY, is the time from starting free
oscillation of VDS to power MOSFET turn-on. The
Figure 9-6 FB/OLP pin peripheral circuit tONDLY of an ideal bottom-on operation is half cycle of
the free oscillation, and is calculated using Equation (3).

Target voltage t ONDLY ≒ π L P × C V (3)

- VSC
VF
T1 D51
+ VROCP
LP
VFLY VO
Voltage on both P S IOFF
FB Comparator C1 ID C51
sides of ROCP VIN
NP NS
Drain current,
ID CV
U1

Figure 9-7 Drain current, ID, and FB comparator

operation in steady operation Figure 9-8 Basic flyback converter circuit

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Table 9-1 The meaning of symbols in Figure 9-8 The threshold voltage of quasi-resonant operation has
a hysteresis. VBD(TH1) is Quasi-Resonant Operation
Symbol Descriptions Threshold Voltage 1, VBD(TH2) is Quasi-Resonant
VIN Input voltage Operation Threshold Voltage 2.
VFLY Flyback voltage When the BD pin voltage, VREV2, increases to
VFLY = P × (VO + VF )
N VBD(TH1) = 0.24 V or more at the power MOSFET
NS turns-off, the power MOSFET keeps the off-state. After
VDS The voltage between Drain and Source of that, the VDS decreases by the free oscillation. When the
power MOSFET VDS decreases to VBD(TH2) = 0.17 V, the power MOSFET
NP Primary side number of turns turns-on and the threshold voltage goes up to VBD(TH1)
NS Secondary side number of turns automatically to prevent malfunction of the BD pin from
noise interference.
VO Output voltage
VF Forward voltage drop of the secondary
T1
side rectifier
P
ID Drain current of power MOSFET VIN C1
VIN VFLY
IOFF Current which flows through the
secondary side rectifier when power
MOSFET is off D2 R2
D
CV Voltage resonant capacitor CV VREV1 VFW1
LP Primary side inductance C3
1 3
D/ST VCC
tONDLY U1 DZBD Forward voltage
Flyback voltage
VFLY RBD1
6
BD
VIN 2 S/OCP GND
R 4 VREV2
VDS 0 OCP CBD RBD2
Bottom point

Figure 9-10 BD pin peripheral circuit

IOFF 0

Auxiliary
ID 0
winding
tON voltage, VD
VREV1
0
Figure 9-9 Ideal bottom-on operation waveform
VFW1

9.7.2 Bottom-On Timing Setup

3.0 V recommended,
BD pin detects the signal of bottom-on timing and but less than 6.0 V acceptable tON
input compensation of OCP1 (refer to Section 9.12.3).
Quasi-resonant
Figure 9-10 shows the BD pin peripheral circuit, Figure Signal, VREV2 VBD(TH1)
9-11 shows the waveform of auxiliary winding voltage. VBD(TH2)
The quasi-resonant signal, VREV2, is proportional to 0
auxiliary winding voltage, VD and is calculated as
follows:
Figure 9-11 The waveform of auxiliary winding voltage

× (VREV1 − VF )
R BD 2
VREV 2 = (4)  RBD1 and RBD2 Setup
R BD1 + R BD 2
RBD1 and RBD2 should be set so that VREV2 becomes
the following range:
where, Under the lowest condition of VCC pin voltage in
VREV1: Flyback voltage of auxiliary winding D power supply specification, VREV2 ≥ VBD(TH1)= 0.34
VF : Forward voltage drop of ZBD V(max.).
Under the highest condition of VCC pin voltage in
The BD pin detects the bottom point using the VREV2.

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power supply specification, VREV2 < 6.0 V (Absolute In the converse situation, if the turn-on point lags
maximum rating of the BD pin) and the effective behind the VDS bottom point (Figure 9-14), after
pulse width of quasi-resonant signal is 1.0 μs or more confirming the initial turn-on point, advance the
(refer to Figure 9-12). turn-on point by decreasing the CBD value gradually,
The value of VREV2 is recommended about 3.0 V. so that the turn-on will match the bottom point of VDS.

3.0 V recommended,
Quasi-resonant
but less than 6.0 V acceptable
Delayed turn-on point
signal, VREV2

0.34V

0.27V VDS 0
Bottom point
Effective pulse width
(1.0μs or more) IOFF 0

Figure 9-12 The effective pulse width

of quasi-resonant signal ID 0
ｔON

 CBD Setup VBD(TH1)

VBD 0 VBD(TH2)
The delay time, tONDLY, until which the power Auxiliary
MOSFET turns on, is adjusted by the value of CBD, so winding voltage
that the power MOSFET turns on at the bottom-on of
VDS (refer to Figure 9-9). VD 0
The initial value of CBD is set about 1000 pF. CBD is
adjusted while observing the actual operation
waveforms of VDS and ID under the maximum input
voltage and the maximum output power (If a voltage
Figure 9-14 When the turn-on of a VDS waveform occurs
probe is connected to BD pin, the bottom point may
after a bottom point
misalign).
If the turn-on point precedes the bottom of the VDS
signal (see Figure 9-13), after confirming the initial
turn-on point, delay the turn-on point by increasing 9.8 BD Pin Blanking Time
the CBD value gradually, so that the turn-on will match Since the auxiliary winding voltage is input to the BD
the bottom point of VDS. pin, BD pin voltage may be affected from the surge
voltage ringing when the power MOSFET turns off. If
Early turn-on point the IC detects the surge voltage as quasi-resonant signal,
the IC may repeatedly turn the power MOSFET on and
off at high frequency. This result in an increase of the
MOSFET power dissipation and temperature, and it can
VDS 0
be damaged.
Bottom point The BD pin has a blanking period of 250 ns (max.) to
avoid detecting voltage during this period.
IOFF 0 The poor coupling (the high leakage inductance) tends
to happen in a low output voltage transformer design
with high NP/ NS turns ratio (NP and NS indicate the
ID 0 number of turns of the primary winding and secondary
ｔON winding, respectively), and the surge voltage ringing of
BD pin occurs easily (see Figure 9-15).
VBD(TH1)
VBD(TH2) If the surge voltage continues longer than BD pin
VBD 0
blanking period and the high frequency operation of
Auxiliary
winding voltage power MOSFET occurs, the following adjustments are
required so that the surge period of BD pin is less than
VD 0 250 ns.
In addition, the BD pin waveform during operation
should be measured by connecting test probes as short to
the BD pin and the GND pin as possible, in order to
Figure 9-13 When the turn-on of a VDS waveform occurs measure any surge voltage correctly.
before a bottom point

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 CBD must be connected near the BD pin and the GND and this enables the IC to switch in a stable operation.
pin. Before the one bottom-skip point changed from heavy
 The circuit trace loop between the BD pin and the to light load, or after that done from light to heavy load,
GND pin must be separated from any traces carrying the switching frequency of the normal quasi-resonant
high current operation becomes higher and the switching loss of
 The coupling of the primary winding and the auxiliary power MOSFET increases. Thus, the temperature of the
winding must be good power MOSFET should be checked at higher switching
 The clamping snubber circuit (refer to Figure 6-1) frequency of the operation changing point in maximum
must be adjusted properly. AC input voltage.

One bottom-skip quasi-resonant

VBD(TH1) VOCP(H)
VBD(TH2) VOCP(BS1)
VREV2

(a)Normal BD pin waveform (good coupling)

Normal quasi-resonant
VOCP(BS2)

VBD(TH1) Load current

VBD(TH2)
VREV2
Figure 9-16 Hysteresis at the operational mode change
BD pin blanking time 250ns（max.）

(b)Inappropriate BD pin waveform (poor coupling)  The mode is changed from one bottom-skip
quasi-resonant operation to normal quasi-resonant
operation (light load to heavy load).
Figure 9-15 The difference of BD pin voltage, VREV2, When load is increased from one bottom-skip
waveform by the coupling condition of the transformer operation, the MOSFET peak drain current value will
increase, and the positive pulse width will widen.
Also, the peak value of the S/OCP pin voltage
9.9 Multi-mode Control increases. When the load is increased further and the
When the output power decreases, the usual S/OCP pin voltage rises to VOCP(BS1), the mode is
quasi-resonant control increases the switching frequency changed to normal quasi-resonant operation (see
and the switching loss. Figure 9-17).
Thus, The IC has the multi-mode control to achieve
One bottom-skip Normal
high efficiency operation across the full range of loads. quasi-resonant quasi-resonant
The automatic multi-mode control changes among the VDS
following three operational modes according to the
output loading state: normal quasi-resonant operation in
heavy load, one bottom-skip quasi-resonant operation in
VOCP(H)
medium to light load, and burst oscillation operation
S/OCP VOCP(BS1)
(auto standby function) in light load. pin voltage

Light load Heavy load

9.9.1 One Bottom-Skip Quasi-Resonant
Operation
Figure 9-17 Operation state transition diagram from
The one bottom-skip function limits the rise of the light load to heavy load conditions
power MOSFET operation frequency in medium to light
load in order to reduce the switching loss.
Figure 9-17 shows the operation state transition  The mode is changed from normal quasi-resonant
diagram of the output load from light load to heavy load. operation to one bottom-skip quasi-resonant operation
Figure 9-18 shows the state transition diagram from (heavy load to light load).
heavy load to light load. When load is decreased from normal quasi-resonant
As shown in Figure 9-16, in the process of the operation, the MOSFET peak drain current value will
increase and decrease of load current, hysteresis is decrease, and the positive pulse width will narrow.
imposed at the time of each operational mode change. Also, the peak value of the S/OCP pin voltage
For this reason, the switching waveform does not decreases. When load is reduced further and the
become unstable near the threshold voltage of a change, S/OCP pin voltage falls to VOCP(BS2), the mode is

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changed to one bottom-skip quasi-resonant operation 9.9.2 Automatic Standby Mode Function
(see Figure 9-18).
The S/OCP pin circuit monitors ID. Automatic
Normal One bottom-skip standby mode is activated automatically when ID reduces
VDS
quasi-resonant quasi-resonant under light load conditions at which the S/OCP pin
voltage falls to the standby state threshold voltage (about
9% compared to VOCP(H) = 0.910 V).
During standby mode, when the FB/OLP pin voltage
VOCP(H) falls below VFB(STBOP), the IC stops switching operation,
S/OCP and the burst oscillation mode will begin, as shown in
pin
voltage
VOCP(BS2) Figure 9-21.
Burst oscillation mode reduces switching losses and
improves power supply efficiency because of periodic
Heavy load Light load
non-switching intervals.
Generally, to improve efficiency under light load
Figure 9-18 Operation state transition diagram from conditions, the frequency of the burst oscillation mode
heavy load to light load conditions becomes just a few kilohertz. Because the IC suppresses
the peak drain current well during burst oscillation mode,
audible noises can be reduced.
Figure 9-19 shows the effective pulse width of normal
If the VCC pin voltage decreases to VCC(BIAS) = 11.0 V
quasi-resonant signal, and Figure 9-20 shows the
during the transition to the burst oscillation mode, the
effective pulse width of one bottom-skip quasi-resonant
Bias Assist function is activated and stabilizes the
signal. In order to perform stable normal quasi-resonant
Standby mode operation, because ICC(STARTUP) is
operation and one bottom-skip operation, it is necessary
provided to the VCC pin so that the VCC pin voltage
to ensure that the pulse width of the quasi-resonant
does not decrease to VCC(OFF).
signal is 1 μs or more under the conditions of minimum
However, if the Bias Assist function is always
input voltage and minimum output power.
activated during steady-state operation including
The pulse width of the quasi-resonant signal, VREV2, is
standby mode, the power loss increases. Therefore, the
defined as the period from the maximum specification of
VCC pin voltage should be more than VCC(BIAS), for
VBD(TH1), 0.34 V, on the rising edge, to the maximum
example, by adjusting the turns ratio of the auxiliary
specification of VBD(TH2), 0.27 V on the falling edge of
winding and secondary winding and/or reducing the
the pulse.
value of R2 in Figure 10-2 (refer to Section 10.1
Quasi-resonant
Peripheral Components for a detail of R2).
signal, VREV2
Output current, Burst oscillation
0.34V IOUT

0.27V

S/OCP pin
Below several kHz
Effective pulse width
voltage 1.0µs or more
Drain current,
ID

Figure 9-19 The effective pulse width of normal Normal Standby Normal
quasi-resonant signal operation operation operation

Figure 9-21 Auto Standby mode timing

Quasi-resonant
signal, VREV2

0.34V
9.10 Maximum On-Time Limitation
Function
0.27V
When the input voltage is low or in a transient state
Effective pulse width
such that the input voltage turns on or off, the on-time of
S/OCP pin
voltage 1.0µs or more the incorporated power MOSFET is limited to the
maximum on-time, tON(MAX) = 40.0 μs in order to prevent
the decreasing of switching frequency. Thus, the peak
Figure 9-20 The effective pulse width of one drain current is limited, and the audible noise of the
bottom-skip quasi-resonant signal transformer is suppressed.
In designing a power supply, the on-time must be less

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than tON(MAX) (see Figure 9-22). In addition, if a C (RC) damper snubber of Figure
If such a transformer is used that the on-time is 9-24 is used, reduce the capacitor value of damper
tON(MAX) or more, under the condition with the minimum snubber. If the turn-on timing isn’t fitted to a VDS bottom
input voltage and the maximum output power, the output point, adjustments are required (refer to Section 9.7.2).
power would become low. In that case, the transformer
should be redesigned taking into consideration the C（CR）
following: damper snubber
T1
 Inductance, LP, of the transformer should be lowered
in order to raise the operation frequency. D51
C1 C51
 Lower the primary and the secondary turns ratio, NP /
NS, to lower the duty cycle. 1
D/ST

ID On-time U1 C（CR）
S/OCP damper snubber
2

ROCP
time
VDS

Figure 9-24 Damper snubber circuit

time

9.11.2 Overcurrent Protection 2 (OCP2)

Figure 9-22 Confirmation of maximum on-time
The products with the last letter "A" don’t have the
OCP2 function.
9.11 Overcurrent Protection (OCP) As the protection for an abnormal state, such as an
output winding being shorted or the withstand voltage of
The IC has an Overcurrent Protection 1 (OCP1) and secondary rectifier being out of specification, when the
an Overcurrent Protection 2 (OCP2). S/OCP pin voltage reaches VOCP(La.OFF) = 1.83 V, the IC
OCP1 function: pulse-by-pulse, with Input Compen- stops switching operation immediately, in latch mode.
sation Function. The OCP2 function: In case output This overcurrent protection also operates during the
winding is shorted etc., the IC stops switching operation leading edge blanking.
at the latched state. The products with the last letter "A" Releasing the latched state is done by turning off the
don’t have the OCP2 function. input voltage and by dropping the VCC pin voltage
below VCC(OFF).

9.11.1 Overcurrent Protection 1 (OCP1)

OCP1 detects each drain peak current level of a power 9.11.3 OCP1 Input Compensation Function
MOSFET on pulse-by-pulse basis, and limits the output The usual control ICs have some propagation delay
power when the current level reaches to OCP threshold time. The steeper the slope of the actual drain current at
voltage. During Leading Edge Blanking Time (tBW), a high AC input voltage is, the larger the detection
OCP1 is disabled. When power MOSFET turns on, the voltage of actual drain peak current is, compared to
surge voltage width of S/OCP pin should be less than overcurrent detection threshold voltage. Thus, the peak
tON(LEB), as shown in Figure 9-23. In order to prevent current has some variation depending on the AC input
surge voltage, pay extra attention to ROCP trace layout voltage in OCP1 state.
(refer to Section 10.3). When using a quasi-resonant converter with universal
input (85 to 265 VAC), if the output power is set
tON(LEB) constant, then because higher input voltages have higher
frequency, the on-time is reduced. Thus, the peak
VOCP(H)’ current in OCP1 state tends to be affected by
propagation delay in the higher input voltage.
If the IC does not have Input Compensation Function,
the output current at OCP1 point in the maximum input
voltage, IOUT(OCP), becomes about double of IOUT (Figure
Surge at MOSFET turn on 9-25 “without input compensation”). IOUT is the target
output current considered with maximum output power
Figure 9-23 S/OCP pin voltage in the minimum input voltage.

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In order to suppress this variability, this IC has the When VDZBD < VFW1 (Point B through Point D), the
overcurrent input compensation function. input voltage is increased and VFW1 exceeds the Zener
voltage, VZ, of DZBD. VFW2 will be produced as a
negative voltage to compensate VOCP(H).
Without input The value of VFW2 should be adjusted so that the
compensation
Output Current at OCP1

difference between IOUT and IOUT(OCP) is minimized as

shown in Figure 9-25 “With optimal input compen-
IOUT(OCP) （A）

With optimal input

compensation sation”. If the excessive input compensation, IOUT(OCP)
IOUT may become less than IOUT (Figure 9-25 “With excessive
Target output current
input compensation”). Thus, value of VFW2 must be
With excessive adjusted so that IOUT(OCP) remains more than IOUT, across
input compensation the input voltage range.
85V 265V
AC input voltage （V）
VAC
230
100
Figure 9-25 OCP1 input compensation 0
Auxiliary
winding
Figure 9-26 shows the OCP1 input compensation voltage VREV1
0
circuit. The value of input compensation is set by BD
pin peripheral circuit. VFW1
By OCP1 Input Compensation Function, Overcurrent
VDZBD
Detection 1 Threshold Voltage in Normal Operation,
0
VOCP(H) = 0.910 V, is compensated depending on an AC
input voltage. VZ
The forward voltage of auxiliary winding D, VFW1, is VFW2
proportional to AC input voltage. As shown in Figure
0
9-26, the voltage obtained by subtracting zener voltage, A
VZ, of DZBD from VFW1 is biased by either end of RBD1 B
C
and RBD2, and thus the BD pin voltage is provided the D
voltage on RDB2 divided by the divider of RBD1 and RBD2. At the input voltage where VFW1 reaches VZ
or more, VFW2 goes negative.
Flyback voltage, VREV1
D2 Figure 9-27 Each voltage waveform for the input voltage
R2 T1
in normal quasi-resonant operation
C3
3 D Setup of BD pin peripheral components (DZBD, RBD1
VCC and RBD2) is as follows:
DZBD Forward voltage
VDZBD V
FW1
1) VIN(AC)C Setup
VIN(AC)C is the AC input voltage that starts input
RBD1
compensation. In general specification, VIN(AC)C is
6 set 120 VAC to 170 VAC.
BD
S/OCP GND
2 4 VFW2 2) VZ Setup
RBD2
ROCP CBD VIN(AC)C is adjusted by the zener voltage, VZ, of
DZBD. The VFW1 at VIN(AC)C is calculated by using
Equation (5). VZ is set from the result.

Figure 9-26 OCP input compensation circuit ND

VFW1 = × VIN ( AC) C × 2 = VZ (5)
NP
Figure 9-27 shows the each voltage waveform for the
input voltage in normal quasi-resonant operation. where,
When VDZBD ≥ VFW1 (Point A), No input NP: Primary side number of turns
compensation required, VFW2 remains zero, and the ND: Secondary side number of turns
detection voltage for an overcurrent event is the
Overcurrent 1 Detection Threshold Voltage in Normal
Operation, VOCP(H).

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3) RBD1 and RBD2 Setup. 5) VREV2 is calculated by using Equation (8) and is
The recommended value of RBD2 is 1.0 kΩ. checked to be the Quasi-Resonant Operation
In general specification, RBD1 is set by using result of Threshold Voltage 1, VBD(TH1) = 0.34 V (max.), or
Equation (6) so that VFW2 = −3.0 V at maximum AC more (refer to Figure 9-11).
input voltage.

× (VREV1 − VF ) ≥ 0.34 V
R BD 2
VREV 2 = (8)
R BD1
R
= BD 2
R BD1 + R BD 2
VFW 2
(6) where,
N 
×  D × VIN ( AC) MAX × 2 − VZ − VFW 2  VREV1: Flyback voltage of auxiliary wining
 NP  VF: Forward voltage drop of DZBD

where,
VFW2: BD pin voltage (−3.0 V) 6) The BD pin voltage, which includes surge voltage,
NP: Primary side winding number of turns must be observed within the absolute maximum
ND: Auxiliary winding number of turns rating of the BD pin voltage (–6.0 to 6.0 V) in the
VIN(AC)MAX: Maximum AC input voltage actual operation at the maximum input voltage.
VZ: Zener voltage of DZBD
4) VOCP(H)' is the overcurrent threshold voltage after
< BD Pin Peripheral Components Value Selection
input compensation. Figure 9-28 shows a
Reference Example >
relationship of VOCP(H)' and BD pin voltage,VFW2.
Setting value:
VFW2 at maximum AC input voltage is calculated by
Input voltage: VIN(AC) = 85VAC to 265VAC,
using Equation (7). VOCP(H)' and this variation are
AC input voltage that starts input compensation:
gotten by using the result from Figure 9-28.
VIN(AC)C = 120 VAC,
When VOCP(H)' including variation becomes the
Primary side winding number of turns: NP = 40 T,
Bottom-Skip Operation Threshold Voltage 1,
Auxiliary winding number of turns: ND = 5 T
VOCP(BS1) = 0.572 V, or less, the operation of IC is
Forward voltage of auxiliary winding: VFW1 = 20 V
one bottom-skip only and the output current may be
less than target output current, IOUT.
VFW1 is calculated by using Equation (5) as follows:

× ( VFW1 − VZ )
R BD 2
VFW 2 = ND
R BD1 + R BD 2 VFW1 = × VIN ( AC) C × 2
NP

R BD 2  N  =
5
× 120 2 = 21.2V
= ×  D × VIN ( AC) MAX × 2 − VZ  (7)
R BD1 + R BD 2  N  40
 P 
Thus, zener voltage of DZBD is chosen to be 22 V of
the E series.
1 When VFW2 = −3.0 V at maximum input voltage,
VOCP(H) 265VAC, RBD1 is calculated by using Equation (6) as
0.8 follows:

0.6 R BD 2  N D 
VOCP(H)' (V)

R BD1 = × × VIN ( AC) MAX × 2－VZ − VFW 2 

VFW 2  N P
Max.

0.4 Typ.
Min. 1k  5 
= ×  × 265 2 − 22 − − 3  = 7.28kΩ
0.2 − 3  40 
0
00 −1
-1 −2
-2 −3
-3 −4
-4 −5
-5 −6
-6 Thus, RBD1 is chosen to be 7.5 kΩ of the E series.
BD pin voltage VFW2 (V)

Figure 9-28 Overcurrent threshold voltage after input

compensation, VOCP(H)'
(reference for design target values)

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When RBD2 = 1.0 kΩ, |VFW2| value at 265 VAC is When the peak drain current of ID is limited by
calculated by using Equation (7) as follows: Overcurrent Protection 1 operation, the output voltage,
VOUT, decreases and the feedback current from the

× ( VFW1 − VZ )
R BD 2 secondary photo-coupler becomes zero. Thus, the
VFW 2 = feedback current, IFB, charges C4 connected to the
R BD1 + R BD 2
FB/OLP pin and the FB/OLP pin voltage, VFB/OLP,
increases.
1k  5  When VFB/OLP increases to the FB Pin Maximum
= ×  × 265 2 − 22  = 2.92V
7.5k + 1k  40  Voltage in Feedback Operation, VFB(MAX) = 4.05 V, or
more, C4 is charged by IFB(OLP) = − 10 µA. When VFB/OLP
increases to the OLP Threshold Voltage, VFB(OLP) = 5.96
Referring to Figure 9-28, when VFW2 is compensated V, the OLP function is activated, the IC stops switching
to –2.92 V, the overcurrent threshold voltage after input operation in the latched state. In order to keep the
compensation, VOCP(H)', is set to about 0.66 V (typ). latched state, when VCC pin voltage decreases to
When setting RBD2 = 1.0 kΩ, RBD1 = 7.5 kΩ, VCC(BIAS), the bias assist function is activated and VCC
VF = 0.7 V, and VREV1 = 20 V, VREV2 is calculated by pin voltage is kept to over the VCC(OFF).
using Equation (8) as follows: Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
× (VREV1 − VF )
R BD 2 below VCC(OFF).
VREV 2 =
R BD1 + R BD 2

GND FB/OLP
× (20 − 0.7 ) = 2.27 V
1k
=
1k + 7.5k 4 5

VREV2 is VBD(TH1) = 0.34 V (max.) or more. IFB

R3
C5 PC1
C4
9.11.4 When Overcurrent Input
Compensation is Not Required
When the input voltage is narrow range, or provided
Figure 9-29 FB/OLP pin peripheral circuit
from PFC circuit, the variation of the input voltage is
small. Thus, the variation of OCP point may become
less than that of the universal input voltage specification.
VCC pin voltage AC input voltage off
When overcurrent input compensation is not required,
VCC(BIAS) Latch release
the input compensation function can be disabled by
substituting a high-speed diode for the zener diode, VCC(OFF)
DZBD, and by keeping BD pin voltage from being minus
voltage. In addition, Equation (9) shows the reverse FB/OLP pin
voltage of a high-speed diode. The peak reverse voltage voltage, VFB/OLP Charged by IFB(OLP)
VFB(OLP)
of high-speed diode selection should take account of its
VFB(MAX)
derating.

ND tDLY
VFW1 = × VIN ( AC) MAX × 2 (9) Drain current, ID
NP

where,
VFW1: Forward voltage of auxiliary wining
NP: Primary side number of turns Figure 9-30 OLP operation waveforms
ND: Secondary side number of turns
VIN(AC)MAX: Maximum AC input voltage
The time of the FB/OLP pin voltage from VFB(MAX) to
VFB(OLP) is defined as the OLP delay time, tDLY. Because
the capacitor C5 for phase compensation is small
9.12 Overload Protection (OLP) compared to C4, the approximate value of tDLY is
Figure 9-29 shows the FB/OLP pin peripheral circuit, calculated by Equation (10). When C4 = 4.7 μF, the
Figure 9-29 shows each waveform for Overload value of tDLY would be approximately 0.9 s. The
Protection (OLP) operation. recommended value of R3 is 47 kΩ.

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9.13 Overvoltage Protection (OVP)

t DLY ≒
(V FB ( OLP ) )
− VFB( MAX ) × C4
When a voltage between VCC pin and GND pin
I FB( OLP ) increases to VCC(OVP) = 31.5 V or more, Overvoltage
Protection (OVP) is activated, the IC stops switching

t DLY ≒
(5.96V − 4.05V )× C4 operation at the latched state. In order to keep the
(10) latched state, when VCC pin voltage decreases to
− 10µΑ
VCC(BIAS), the bias assist function is activated and VCC
pin voltage is kept to over the VCC(OFF).
To enable the overload protection function to initiate Releasing the latched state is done by turning off the
an automatic restart, 220 kΩ is connected between the input voltage and by dropping the VCC pin voltage
FB/OLP pin and ground, as a bypass path for IFB(OLP), as below VCC(OFF).
shown in Figure 9-31. Thus, the FB/OLP pin is kept When the VCC pin voltage is provided by using
under VFB(OLP) in OLP state. auxiliary winding of transformer, the overvoltage
In OLP state as an output shorted, the output voltage conditions such as output voltage detection circuit open
and VCC pin voltage decrease. During the operation, can be detected because the VCC pin voltage is
Bias Assist Function is disabled. Thus, VCC pin voltage proportional to output voltage. The approximate value of
decreases to VCC(OFF), the control circuit stops operation. output voltage VOUT(OVP) in OVP condition is calculated
After that, the IC reverts to the initial state by UVLO by using Equation (11).
circuit, and the IC starts operation when VCC pin
voltage increases to VCC(ON) by startup current. Thus the VOUT ( NORMAL)
intermittent operation by UVLO is repeated in OLP state VOUT(OVP) = × 31.5 (V) (11)
without latched operation as shown in Figure 9-32. VCC ( NORMAL)
The intermittent oscillation is determined by the cycle
of the charge and discharge of the capacitor C3 where,
connected to the VCC pin. In this case, the charge time VOUT(NORMAL): Output voltage in normal operation
is determined by the startup current from the startup VCC(NORMAL): VCC pin voltage in normal operation
circuit, while the discharge time is determined by the
current supply to the internal circuits of the IC.
9.14 Thermal Shutdown (TSD)
GND FB/OLP When the temperature of control circuit increases to
Tj(TSD) = 135 °C (min.) or more, Thermal Shutdown
4 5 (TSD) is activated, the IC stops switching operation at
the latched state. In order to keep the latched state, when
IFB PC1 VCC pin voltage decreases to VCC(BIAS), the bias assist
C5 function is activated and VCC pin voltage is kept to over
220kΩ
the VCC(OFF).

Figure 9-31 FB/OLP pin peripheral circuit

(without latched operation)

VCC pin
voltage
VCC(ON)
VCC(OFF)

FB/OLP pin
voltage
VFB(OLP)

Drain current,
ID

Figure 9-32 OLP operation waveform at output shorted

(without latched operation)

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10. Design Notes transformer matching what will be used in the actual
application, because the variation of the auxiliary
winding voltage is affected by the transformer
structural design.
10.1 External Components
Take care to use properly rated, including derating as
necessary and proper type of components. VCC pin voltage Without R2

BR1 CRD clamp snubber

T1
VAC
C1 C2 R1 P

D1 With R2
U1 D2 R2
Output current, IOUT
C3 D
FB/OLP
S/OCP
D/ST

GND
VCC

Figure 10-2 Variation of VCC pin voltage and power

BD
NF

DZBD
2

1 2 3 4 5 6 7
CV RBD1
• FB/OLP Pin Peripheral Circuit
C5 is for high frequency noise reduction and phase
C(RC) damper
snubber R3
RBD2
compensation, and should be connected close to these
ROCP
C5 PC1
CBD pins. The value of C5 is recommended to be about
C4
470 pF to 0.01µF, and should be selected based on
actual operation in the application.
C4 is for the OLP delay time, tDLY, setting (refer to
Figure 10-1 The IC peripheral circuit Section 9.13).
The recommended value of R3 is 47 kΩ.
• Input and Output Electrolytic Capacitor
Apply proper derating to ripple current, voltage, and • BD Pin Peripheral Circuit
temperature rise. Use of high ripple current and low Since BD pin detects the signal of bottom-on
impedance types, designed for switch mode power timing and input compensation of OCP1, the values
supplies, is recommended. of BD pin peripheral components (DZBD, RBD1, RBD2
and CBD) are considered about both functions and
• S/OCP Pin Peripheral Circuit should be adjusted.
In Figure 10-1, ROCP is the resistor for the current Refer to Section 9.7.2 and Section 9.12.3.
detection. A high frequency switching current flows
to ROCP, and may cause poor operation if a high • NF Pin
inductance resistor is used. Choose a low inductance For stable operation, NF pin should be connected to
and high surge-tolerant type. GND pin, using the shortest possible path.

• VCC Pin Peripheral Circuit • Snubber Circuit

The value of C3 in Figure 10-1 is generally When the surge voltage of VDS is large, the circuit
recommended to be 10µ to 47μF (refer to Section 9.1 should be added as follows (see Figure 10-1);
Startup Operation”, because the startup time is
determined by the value of C3). ・ A clamp snubber circuit of a capacitor-resistor-
In actual power supply circuits, there are cases in diode (CRD) combination should be added on the
which the VCC pin voltage fluctuates in proportion to primary winding P.
the output current, IOUT (see Figure 10-2), and the ・ A damper snubber circuit of a capacitor (C) or a
Overvoltage Protection function (OVP) on the VCC resistor-capacitor (RC) combination should be
pin may be activated. This happens because C3 is added between the D/ST pin and the S/OCP pin.
charged to a peak voltage on the auxiliary winding D, When the damper snubber circuit is added, this
which is caused by the transient surge voltage coupled components should be connected near D/ST pin
from the primary winding when the power MOSFET and S/OCP pin.
turns off.
For alleviating C3 peak charging, it is effective to add • Peripheral Circuit of Secondary Side Shunt
some value R2, of several tenths of ohms to several Regulator
ohms, in series with D2 (see Figure 10-1). The Figure 10-3 shows the secondary side detection circuit
optimal value of R2 should be determined using a with the standard shunt regulator IC (U51).

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C52 and R53 are for phase compensation. The value should be maximized.
of C52 and R53 are recommended to be around 0.047 ▫ The coupling of the winding D and the winding P
μF to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively. should be minimized.
They should be selected based on actual operation in
the application. In the case of multi-output power supply, the
coupling of the secondary-side stabilized output
winding, S1, and the others (S2, S3…) should be
L51 maximized to improve the line-regulation of those
T1 D51 VOUT
outputs.
(+)
Figure 10-4 shows the winding structural examples
R54 of two outputs.
Winding structural example (a):
PC1 R51
S1 is sandwiched between P1 and P2 to
R55 maximize the coupling of them for surge
C51
reduction of P1 and P2.
S R52 C53 D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of
C52 R53 D.
Winding structural example (b)
U51 P1 and P2 are placed close to S1 to maximize the
R56 coupling of S1 for surge reduction of P1 and P2.
(-) D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2.
This structure reduces the surge of D, and
Figure 10-3 Peripheral circuit of secondary side shunt improves the line-regulation of outputs.
regulator (U51)

• Transformer Margin tape

Apply proper design margin to core temperature rise
by core loss and copper loss.
Bobbin

P1 S1 P2 S2 D
Because the switching currents contain high
frequency currents, the skin effect may become a Margin tape
consideration.
Choose a suitable wire gauge in consideration of the Winding structural example (a)
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
Margin tape
necessary, the following should be considered to
increase the total surface area of the wiring:
Bobbin

▫ Increase the number of wires in parallel. P1 S1 D S2 S1 P2

▫ Use litz wires.
▫ Thicken the wire gauge. Margin tape

In the following cases, the surge of VCC pin Winding structural example (b)
voltage becomes high.
▫ The surge voltage of primary main winding, P, is Figure 10-4 Winding structural examples
high (low output voltage and high output current
power supply designs)
▫ The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.

When the surge voltage of winding D is high, the

VCC pin voltage increases and the Overvoltage
Protection function (OVP) may be activated. In
transformer design, the following should be
considered;
▫ The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
▫ The coupling of the winding D and the winding S

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10.2 Transformer Design where,

VIN(MIN) : C1 voltage at the minimum AC input voltage
The design of the transformer is fundamentally the DON: On-duty at the minimum input voltage
same as the power transformer of a Ringing Choke PO: maximum output power
Converter (RCC) system: a self-excitation type flyback fMIN: minimum operation frequency
converter. However, because the duty cycle will change η1: transformer efficiency
due to the quasi-resonant operations delaying the turn-on, CV: the voltage resonance capacitor connected
the duty cycle needs to be compensated. between the drain and source of the power MOSFET
Figure 10-5 shows the quasi-resonant circuit.
Each parameter, such as the peak drain current, IDP, is
VF calculated by the following formulas:
T1 D51
LP
VFLY VO t ONDLY = π L P '×C V (15)
P S IOFF
C1 ID C51
D ON ' = D ON (1 − f MIN × t ONDLY )
VIN
NP NS (16)

CV PO 1
U1 I IN = × (17)
η2 VIN(MIN)

2 × I IN
Figure 10-5 Quasi-resonant circuit I DP = (18)
D ON '

The flyback voltage, VFLY is calculated as follows:

LP '
NP = (19)
Al‐value
= P × (VO + VF )
N
VFLY (12)
NS
N P × (VO + VF )
NS = (20)
where, VFLY
NP: Primary side number of turns
NS: Secondary side number of turns where,
VO: Output voltage tONDLY: Delay time of quasi-resonant operation
VF: Forward voltage drop of D51 IIN: Average input current
η2: conversion efficiency of the power supply
IDP: peak drain current
The on duty, DON, at the minimum AC input voltage DON’: On-duty after compensation
is calculated as follows: VO: Secondary side output voltage

VFLY The minimum operation frequency, fMIN, can be

D ON = (13) calculated by the Equation (22):
VIN ( MIN ) + VFLY

( )
2
 
2PO 4π VIN ( MIN ) × D ON × C V
2
where,  2PO 
VIN(MIN): C1 voltage at the minimum AC input voltage  − + + 
η1 η1 LP'
VFLY: Flyback voltage. f MIN = 
 2π C V × VIN ( MIN ) × D ON 
 
 
The inductance, LP' on the primary side, taking into  
consideration the delay time, is calculated using
Equation (14). (21)

(V )
2
Figure 10-6 shows the Example of NI-Limit versus
× D ON
LP ' = AL-Value characteristics.
IN ( MIN )
2
 2PO × f MIN  (14) Choose the ferrite core that does not saturate and
 + VIN ( MIN ) × D ON × f MIN × π C V  provides a design margin in consideration of
 η1 
  temperature effects and other variations to NI-Limit
versus AL-Value characteristics.

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Al-value is calculated by using LP’ and NP. NI is (2) Control Ground Trace Layout
calculated by using Equation (22). Since the operation of IC may be affected from the
It is recommended that Al-value and NI provide the large current of the main trace that flows in control
design margin of 30 % or more for saturation curve of ground trace, the control ground trace should be
core. separated from main trace and connected at a single
point grounding of point A in Figure 10-7 as close
NI = N P × I DP (AT) (22) to the ROCP pin as possible.

where, (3) VCC Trace Layout

NP: Primary side number of turns This is the trace for supplying power to the IC, and
IDP: Peak switching current thus it should be as small loop as possible. If C3 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
Saturation curve
1.0 μF) close to the VCC pin and the GND pin is
Margin : about 30% recommended.
NI-limit (AT)

(4) ROCP Trace Layout

NI ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure 10-7)
which is close to the base of ROCP.
LP’/NP2
Al-value (nH/T2) (5) Peripheral components of the IC
The components for control connected to the IC
should be placed as close as possible to the IC, and
Figure 10-6 Example of NI-Limit versus AL-Value should be connected as short as possible to the each
characteristics pin.

(6) Secondary Rectifier Smoothing Circuit Trace

10.3 PCB Trace Layout and Component Layout:
Placement This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
Since the PCB circuit trace design and the component as wide trace and small loop as possible. If this trace
layout significantly affects operation, EMI noise, and is thin and long, inductance resulting from the loop
power dissipation, the high frequency PCB trace should may increase surge voltage at turning off the power
be low impedance with small loop and wide trace. MOSFET. Proper rectifier smoothing trace layout
In addition, the ground traces affect radiated EMI noise, helps to increase margin against the power MOSFET
and wide, short traces should be taken into account. breakdown voltage, and reduces stress on the clamp
Figure 10-7 shows the circuit design example. snubber circuit and losses in it.
(1) Main Circuit Trace Layout (7) Thermal Considerations
This is the main trace containing switching currents, Because the power MOSFET has a positive thermal
and thus it should be as wide trace and small loop as coefficient of RDS(ON), consider it in thermal design.
possible. Since the copper area under the IC and the D/ST pin
If C1 and the IC are distant from each other, placing trace act as a heatsink, its traces should be as wide as
a capacitor such as film capacitor (about 0.1 μF and possible.
with proper voltage rating) close to the transformer
or the IC is recommended to reduce impedance of
the high frequency current loop.

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(1) Main trace should be wide (6) Main trace of secondary side should
trace and small loop be wide trace and small loop
T1

D51
C2 R1
C1 P
D1 C51
S
D2 R2
U1 (3) Loop of the power
supply should be small

C3
D
FB/OLP
S/OCP
D/ST

GND
VCC

BD
NF
2

1 2 3 4 5 6 7 DZBD

CV

ROCP
RBD1
C5 PC1
R3 CBD
RBD2
A C4

(7)Trace of D/ST pin (4)ROCP should be as (2) Control GND trace should be CY (5)The components connected to the IC should
should be wide for close to S/OCP connected at a single point as
be as close to the IC as possible, and should
heat release pin as possible. close to the ROCP as possible
be connected as short as possible

Figure 10-7 Peripheral circuit example around the IC

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11. Pattern Layout Example

The following show the four outputs PCB pattern layout example and the schematic of circuit using STR-Y6700
series. The PCB pattern layout example is made usable to other ICs in common. The parts in Figure 11-2 are only used.

Figure 11-1 PCB circuit trace layout example

T1 D50 CN52
1 OUT1(+)

CN1 S1 C50 C53 C58

TH2
2 2 OUT1(-)
RC1 J2 D51
L1 C3 3 OUT2(+)
C4 L51
C1 J53 J54
C51
C6 C12 R7 R8
C2 R50 R57
F1 TH1
1 R58
D6 S2 R52
TK1 P1 C54 C59
PC1 R56
R51 R53 R55
R9 R54 C62

F2 J56 J55
D55 R59
8 OUT2(-)
4 OUT3(+)
D52
D2 D3
S3
C55 C64 C60
IC1 D5 R10
5 OUT3(-)
D1 R4 Q1 J50 J51 J52
D54
STR-Y6700 R5 D 7 OUT4(+)
D10 C8 R6 C11 L50
FB/OLP

D4
S/OCP

S4 C52
D/ST

GND
VCC

C63
BD

C57 C65
NF
2

2 OUT4(-)
1 2 3 4 5 6 7
D7
9 OUT5(+)
R11 D53
C5 S5
C56 C61 J57
R3 PC1 C10 R12 6 OUT5(-)
R1 R2 TK50
C9
C7 C13

Figure 11-2 Circuit schematic for PCB circuit trace layout

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12. Reference Design of Power Supply

 Power supply specification
IC STR-Y6754
Input voltage 85 VAC to 265 VAC
Maximum output power 40.4 W
Output 1 14 V / 2.6A
Output 2 8 V / 0.5 A
 Circuit schematic

D1 D2 T1
D51
L1 S2 S4 OUT1(+)
14V/2.6A
C1 D4 D3
R1 C51 C53
C2 C3 P1
F1
D52
OUT2(+)
8V/0.5A
D5 R51 R54
P2 C52

PC1 R52
R55

U1 D6 C54
R3
R53 C55

STR-Y6700 D
C5 U51
R56
FB/OLP

OUT(-)
S/OCP
D/ST

GND
VCC

S1 S3
BD
NF
2

1 2 3 4 5 6 7 DZ1

R5
C4

R4 PC1 C8 R6
R2
C7 C9
C6

 Bill of materials
Recommended Recommended
Symbol Part type Ratings(1) Symbol Part type Ratings(1)
Sanken Parts Sanken Parts
C1 (2)
Film, X2 0.1 μF, 275 V D52 Schottky 90 V, 1.5 A EK 19
C2 Electrolytic 220 μF, 400 V DZ1 Zener 22V
C3 Ceramic 2200 pF, 630 V F1 Fuse 250 VAC, 3 A
(2)
C4 Ceramic 100 pF, 2 kV L1 CM inductor 3.3 mH
C5 Electrolytic 22 μF, 50V PC1 Photo-coupler PC123or equiv
C6 Ceramic 4.7 μF, 16 V R1 (3)
Metal oxide 150 kΩ, 1 W
C7 (2)
Ceramic 4700 pF, 50V R2 (2)
General 0.56 Ω, 1 W
C8 (2)
Ceramic 470 pF, 50V R3 (2)
General 15 Ω
C9 Ceramic, Y1 2200 pF, 250 V R4 General 47 kΩ
C51 Ceramic 2200 pF, 1 kV R5 (2)
General 6.8 kΩ
C52 Ceramic Open R6 General 1 kΩ
C53 Electrolytic 1000 μF, 50 V R51 General 820 Ω
C54 Electrolytic 470 µF, 16 V R52 General 1.5 kΩ
C55 Ceramic 0.1 µF R53 (2)
General 22 kΩ
D1 General 600V, 1A EM01A R54 (2)
General 6.8 kΩ
D2 General 600V, 1A EM01A R55 General, 1% 39 kΩ
D3 General 600V, 1A EM01A R56 General, 1% 10 kΩ
See
D4 General 600V, 1A EM01A T1 Transformer
the specification
D5 Fast recovery 1000 V, 0.5 A EG01C U1 IC － STR-Y6754
VREF = 2.5 V
D6 Fast recovery 200 V, 1 A AL01Z U51 Shunt regulator
TL431or equiv
D51 Schottky 150 V, 10 A FMEN-210B
(1)
Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2)
It is necessary to be adjusted based on actual operation in the application.
(3)
Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use
combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.

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 Transformer specification
▫ Primary inductance, LP: 0.95 mH
▫ Core size: EER28L
▫ AL-value: 183 nH/N2 (Center gap of about 0.8 mm)
▫ Winding specification
Number of Wire diameter
Winding Symbol Construction
turns (T) (mm)
Two-layer,
Primary winding 1 P1 43 1EUW – φ 0.30
solenoid winding
Single-layer,
Primary winding 2 P2 29 1EUW – φ 0.30
solenoid winding
Single-layer,
Auxiliary winding D 12 TEX – φ 0.23 × 2
Space winding
Single-layer,
Output winding 1 S1 5 φ 0.32 × 2
solenoid winding
Single-layer,
Output winding 2 S2 3 φ 0.32 × 2
solenoid winding
Single-layer,
Output winding 3 S3 5 φ 0.32 × 2
solenoid winding
Single-layer,
Output winding 4 S4 3 φ 0.32 × 2
solenoid winding

OUT1(+)
VDC
14V
P1 S4

P1 P2
S2
S4 S3 D/ST
D VCC OUT2(+)
S2 S1 D S3 8V
P2 GND
Bobbin
S1
Cross-section view OUT(-)
: Start at this pin

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IMPORTANT NOTES
● All data, illustrations, graphs, tables and any other information included in this document as to Sanken’s products listed herein (the
“Sanken Products”) are current as of the date this document is issued. All contents in this document are subject to any change
without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales representative
that the contents set forth in this document reflect the latest revisions before use.
● The Sanken Products are intended for use as components of general purpose electronic equipment or apparatus (such as home
appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Prior to use of the Sanken Products,
please put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them to
Sanken. When considering use of the Sanken Products for any applications that require higher reliability (such as transportation
equipment and its control systems, traffic signal control systems or equipment, disaster/crime alarm systems, various safety
devices, etc.), you must contact a Sanken sales representative to discuss the suitability of such use and put your signature, or affix
your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of the
Sanken Products. The Sanken Products are not intended for use in any applications that require extremely high reliability such as:
aerospace equipment; nuclear power control systems; and medical equipment or systems, whose failure or malfunction may result
in death or serious injury to people, i.e., medical devices in Class III or a higher class as defined by relevant laws of Japan
(collectively, the “Specific Applications”). Sanken assumes no liability or responsibility whatsoever for any and all damages and
losses that may be suffered by you, users or any third party, resulting from the use of the Sanken Products in the Specific
Applications or in manner not in compliance with the instructions set forth herein.
● In the event of using the Sanken Products by either (i) combining other products or materials therewith or (ii) physically,
chemically or otherwise processing or treating the same, you must duly consider all possible risks that may result from all such
uses in advance and proceed therewith at your own responsibility.
● Although Sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid the
occurrence of any failure or defect in semiconductor products at a certain rate. You must take, at your own responsibility,
preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which
the Sanken Products are used, upon due consideration of a failure occurrence rate or derating, etc., in order not to cause any human
injury or death, fire accident or social harm which may result from any failure or malfunction of the Sanken Products. Please refer
to the relevant specification documents and Sanken’s official website in relation to derating.
● No anti-radioactive ray design has been adopted for the Sanken Products.
● No contents in this document can be transcribed or copied without Sanken’s prior written consent.
● The circuit constant, operation examples, circuit examples, pattern layout examples, design examples, recommended examples, all
information and evaluation results based thereon, etc., described in this document are presented for the sole purpose of reference of
use of the Sanken Products and Sanken assumes no responsibility whatsoever for any and all damages and losses that may be
suffered by you, users or any third party, or any possible infringement of any and all property rights including intellectual property
rights and any other rights of you, users or any third party, resulting from the foregoing.
● All technical information described in this document (the “Technical Information”) is presented for the sole purpose of reference
of use of the Sanken Products and no license, express, implied or otherwise, is granted hereby under any intellectual property
rights or any other rights of Sanken.
● Unless otherwise agreed in writing between Sanken and you, Sanken makes no warranty of any kind, whether express or implied,
including, without limitation, any warranty (i) as to the quality or performance of the Sanken Products (such as implied warranty
of merchantability, or implied warranty of fitness for a particular purpose or special environment), (ii) that any Sanken Product is
delivered free of claims of third parties by way of infringement or the like, (iii) that may arise from course of performance, course
of dealing or usage of trade, and (iv) as to any information contained in this document (including its accuracy, usefulness, or
reliability).
● In the event of using the Sanken Products, you must use the same after carefully examining all applicable environmental laws and
regulations that regulate the inclusion or use of any particular controlled substances, including, but not limited to, the EU RoHS
Directive, so as to be in strict compliance with such applicable laws and regulations.
● You must not use the Sanken Products or the Technical Information for the purpose of any military applications or use, including
but not limited to the development of weapons of mass destruction. In the event of exporting the Sanken Products or the Technical
Information, or providing them for non-residents, you must comply with all applicable export control laws and regulations in each
country including the U.S. Export Administration Regulations (EAR) and the Foreign Exchange and Foreign Trade Act of Japan,
and follow the procedures required by such applicable laws and regulations.
● Sanken assumes no responsibility for any troubles, which may occur during the transportation of the Sanken Products including
the falling thereof, out of Sanken’s distribution network.
● Although Sanken has prepared this document with its due care to pursue the accuracy thereof, Sanken does not warrant that it is
error free and Sanken assumes no liability whatsoever for any and all damages and losses which may be suffered by you resulting
from any possible errors or omissions in connection with the contents included herein.
● Please refer to the relevant specification documents in relation to particular precautions when using the Sanken Products, and refer
to our official website in relation to general instructions and directions for using the Sanken Products.

DSGN-CEZ-16001

STR-Y6700 - DS Rev.4.1 SANKEN ELECTRIC CO.,LTD. 33

Jun. 09, 2016