LD7522

1/16/2008

Smart Green-Mode PWM Controller with Multiple Protections

REV:03

General Description Features

The LD7522 is a low startup current, current mode PWM z High-Voltage CMOS Process with Excellent ESD
controller with green-mode power-saving operation. The protection
SOP-8/DIP-8 package integrated functions such as the z Very Low Startup Current (< 35μA)
leading- edge blanking of the current sensing, internal slope z Current Mode Control
z Non-audible-noise Green Mode Control
compensation, line compensation, and several protection
z UVLO (Under Voltage Lockout)
features. The protection functions include cycle-by-cycle
z LEB (Leading-Edge Blanking) on CS Pin
current limit, OVP, OTP, OLP, and brownout protection. It
z Internal Slope Compensation
provides the users a high efficiency, low external component
z Programmable Line Compensation
counts solution for AC/DC power applications. z OVP (Over Voltage Protection)
Furthermore, to satisfy various protection requirements, z OLP (Over Load Protection)
both latch-mode protection and auto-recoverable protection z OTP (Over Temperature Protection) through a NTC
z Brownout Protection
can be easily achieved by configuring LD7522 on different
z Flexibility on Latch/Auto-Recoverable Protection Mode
operation modes.
z 500mA Driving Capability
The special green-mode control is not only to achieve the
low power consumption but also to offer a non-audible-noise Applications
operation when the LD7522 is operating under light load or z Switching AC/DC Adaptor and Battery Charger
no load condition. z Open Frame Switching Power Supply
z LCD Monitor/TV Power
-Patent Pending

Typical Application

AC EMI
input Filter

OVP VCC
7
8 6
OUT
LD7522
1 CS
BNO 4
3 5 2
(-)LATCH GND COMP
photocoupler

TL431

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Pin Configuration
SOP-8 & DIP-8(TOP VIEW)

GND
OVP

VCC
OUT
8 7 6 5

YY : Year code (D: 2004, E: 2005…..)

TOP MARK WW : Week code
YYWWPP ## : Production code

1 2 3 4
(-)LATCH
BNO

COMP

CS

Ordering Information

Part number Package TOP MARK Shipping

LD7522 PS SOP-8 PB Free LD7522PS 2500 /tape & reel

LD7522 GS SOP-8 Green Package LD7522GS 2500 /tape & reel

LD7522 PN DIP-8 DIP-8 LD7522PN 3600/tube /carton

The LD7522 is ROHS Complaint/ Green Package.

Pin Descriptions
PIN NAME FUNCTION
Brownout Protection Pin. Connected a resistor divider from this pin to bulk
1 BNO capacitor voltage to set the brownout level and line compensation. When the
voltage of this pin is lower than threshold voltage, the PWM output will be off.
Voltage feedback pin (same as the COMP pin in UC384X), By connecting a
2 COMP
photo-coupler to close the control loop and achieve the regulation.
Pull this pin to lower than 2.5V will shutdown the controller to the latch mode until
the AC power-on recycling. By connecting a NTC from this pin to ground will
3 (-) LATCH
achieve the OTP protection function. Keep this pin as floating to disable the latch
protection.
4 CS Current sense pin, connect to sense the MOSFET current
5 GND Ground
6 OUT Gate drive output to drive the external MOSFET
7 VCC Supply voltage pin
This pin is high-active to provide the OVP function. By the connecting a zener
or a resistor voltage divider to Vcc will set the OVP level. Whenever the voltage
8 OVP
is higher than 2.5V, the OVP is tripped and the gate drive will be off. Short this
pin to ground to disable the OVP function.

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Block Diagram
VCC

32V

Vbias Vref OK
internal bias
8V
& Vref PG
PDR 16V/10V
100uA Comparator
UVLO
(-) LATCH Comparator VCC OK
3.5V/
2.5V Latch Protection
Comparator

Gain 0 =Enable
BNO = 0.04 1 =Disable
Line S Q
Compensation
5V
1 =Power Down Reset
1.25V R
/1.10V Brownout
Comparator

OVP 1 =OVP
1 = ACUV
S Q
2.5V 1 =OLP
5V OVP
Comparator
PG R
30mS
Delay Auto-Recoverable Protections
5.0V
OLP Latched Protections
Comparator

65KHz
PG
OSC

Driver
PG
Stage
OUT

Green-Mode
Control
Vbias

S Q
PWM
COMP Comparator
2R R
R
+
∑ Slope
Compensation
Leading +
CS Edge
Blanking +
+ Line
∑ Compensation

0.85V
OCP
Comparator

GND

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Absolute Maximum Ratings
Supply Voltage VCC 30V
COMP, CS, (-) LATCH -0.3 ~7V
OVP, BNO -0.3 ~5V
Junction Temperature 150°C
Operating Ambient Temperature -40°C to 85°C
Storage Temperature Range -65°C to 150°C
Package Thermal Resistance (SOP-8) 160°C/W
Package Thermal Resistance (DIP-8) 100°C/W
Power Dissipation (SOP-8, at Ambient Temperature = 85°C) 400mW
Power Dissipation (DIP-8, at Ambient Temperature = 85°C) 650mW
Lead temperature (Soldering, 10sec) 260°C
ESD Voltage Protection, Human Body Model 3KV
ESD Voltage Protection, Machine Model 200V
Gate Output Current 500mA

Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.

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Electrical Characteristics
o
(TA = +25 C unless otherwise stated, VCC=15.0V)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage (VCC Pin)
Startup Current 20 35 μA
VCOMP=0V 3.5 5.0 mA
Operating Current
VCOMP=3V 3.0 mA
(with 1nF load on OUT pin)
Protection Mode (note 1) 0.7 mA
UVLO (off) 9.0 10.0 11.0 V
UVLO (on) 15.0 16.0 17.0 V
Voltage Feedback (Comp Pin)
Short Circuit Current VCOMP=0V 2.5 4.0 mA
Green Mode Threshold VCOMP 2.35 V
Current Sensing (CS Pin)
VBNO=0V (note 2) 0.800 0.850 0.900 V
Maximum Input Voltage, VCS(OFF) VBNO=1.30V 0.748 0.798 0.848 V
VBNO=3.75V 0.650 0.700 0.750 V
Leading Edge Blanking Time 350 nS
Input impedance 1 MΩ
Delay to Output 150 nS
Gate Drive Output (OUT Pin)
Output Low Level VCC=15V, Io=20mA 1.0 V
Output High Level VCC=15V, Io=20mA 9.0 V
Rising Time Load Capacitance=1000pF 50 160 nS
Falling Time Load Capacitance=1000pF 30 60 nS
Oscillator
Frequency 60 65 70 KHz
Green Mode Frequency 20 KHz
Frequency Temp. Stability (-40°C –85°C) 3 %
Frequency Voltage Stability (VCC=12V-30V) 1 %
Latch Protection ((-)LATCH Pin)
(-)LATCH Pin Source Current 92 100 108 μA
Turn-On Trip Level 3.3 3.50 3.7 V
Turn-Off Trip Level 2.40 2.50 2.60 V
(-)LATCH pin de-bounce time 100 μS
De-latch Vcc Level (PDR, Power Down Reset) 6.8 8.0 8.7 V
Note 1: When OVP, OLP, or Latch Protection is tripped.
Note 2: Guaranteed by design because Vcs(off) can’t be measured when VBNO=0V.

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Electrical Characteristics (Continued)
o
(TA = +25 C unless otherwise stated, VCC=15.0V)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Brownout Protection & Line Compensation (BNO Pin)
Brownout Turn-On Trip Level 1.20 1.25 1.30 V
Brownout Turn-Off Trip Level 1.05 1.10 1.15 V
Saturation Voltage on LINE Pin 5.0 V
Line Compensation Ratio 0.04 V/V
Over Voltage Protection (OVP Pin)
OVP Trip Level 2.35 2.50 2.65 V
OVP de-bounce time 100 μS
OLP (Over Load Protection)
OLP Trip Level VCOMP(OLP) 5.0 V
OLP Delay Time VCOMP>5.2V 30 mS

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Typical Performance Characteristics

12.0
18.0

17.2 11.2
UVLO (on) (V)

UVLO (off) (V)

16.4 10.4

15.6 9.6

14.8 8.8

14.0 8.0
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 1 UVLO (on) vs. Temperature Fig. 2 UVLO (off) vs. Temperature

70 26
Green Mode Frequency (KHz)

67 24
Frequency (KHz)

64 22

61 20

58 18

55 16
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 3 Frequency vs. Temperature Fig. 4 Green Mode Frequency vs. Temperature

70 25
Green Mode Frequency (KHz)

68 23
Frequency (KHz)

66 21

64 19

62 17

60 15
12 14 16 18 20 22 24 12 14 16 18 20 22 24
VCC (V)
VCC (V)
Fig. 5 Frequency vs. VCC Fig. 6 Green Mode Frequency vs. VCC

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85 0.90

0.85
80
VLINE= 0V
Max Duty Cycle (%)

0.80
75

VCS (off) (V)

VLINE=1.25V
0.75

70
0.70

VLINE=3.75V
65 0.65

0.60
60
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 7 Max Duty Cycle vs. Temperature Fig. 8 Vcs (off) vs. Temperature

40 2.60

2.55
30
Startup Current (μA)

OVP (V)

2.50
20

2.45
10

0 2.40
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 9 Startup Current vs. Temperature Fig. 10 OVP-Trip Level vs. Temperature

6.0 5.5

5.8 5.3

5.6 5.1
VCOMP (V)

OLP (V)

5.4 4.9

5.2 4.7

5.0 4.5
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 11 VCOMP open-loop voltage vs. Temperature Fig. 12 OLP-Trip Level vs. Temperature

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2.60 110

(-)Latch Pin Source Current (μA)

2.55 100
(-)Latch (V)

2.50 90

2.45 80

2.40 70
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 13 (-)Latch Pin Off-Level vs. Temperature Fig. 14 (-)Latch Pin Source Current vs Temperature

10 10

8 8

6 6
ILINE (μA)

IOVP (μA)

4 4

125°C
2 125°C 2
25°C
25°C
0 0
-40°C
-40°C

-2 -2
0 1 2 3 4 5 0 1 2 3 4 5
VLINE VOVP
Fig. 15 VLINE vs. ILINE Fig. 16 VOVP vs. IOVP

1.27 1.150

1.26 1.125
BNO Pin On (V)

BNO Pin Off (V)

1.25 1.100

1.24 1.075

1.23 1.050
-40 0 40 80 120 -40 0 40 80 120
Temperature (°C) Temperature (°C)
Fig. 17 BNO Pin On Level vs. Temperature Fig. 18 BNO Pin Off Level vs. Temperature

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Application Information
deliver the gate drive signal, the supply current is provided
Operation Overview
from the auxiliary winding of the transformer. Lower
As long as the green power requirement becomes a trend
startup current requirement on the PWM controller will help
and the power saving is getting more and more important for
to increase the value of R1 and then reduce the power
the switching power supplies and switching adapters, the
consumption on R1. By using CMOS process and the
traditional PWM controllers are not able to support such new
special circuit design, the maximum startup current of
requirements. Furthermore, the cost and size limitation force
LD7522 is only 35μA.
the PWM controllers need to be powerful to integrate more
functions to reduce the external part counts. The LD7522 If a higher resistance value of the R1 is chosen, it usually
is targeted on such application to provide an easy and cost takes more time to start up. To carefully select the value of
effective solution; its detail features are described as below: R1 and C1 will optimize the power consumption and startup
time.
Under Voltage Lockout (UVLO)
An UVLO comparator is implemented in it to detect the
voltage on the VCC pin. It would assure the supply voltage
enough to turn on the LD7522 PWM controller and further to
drive the power MOSFET. As shown in Fig. 19, a
hysteresis is built in to prevent the shutdown from the
voltage dip during startup. The turn-on and turn-off
threshold level are set at 16V and 10.0V, respectively.

Vcc

UVLO(on)

UVLO(off)

t
Fig. 20
I(Vcc) operating current
(~ mA)
Output Stage and Maximum Duty-Cycle
An output stage of a CMOS buffer, with typical 500mA
startup current
(~uA) driving capability, is incorporated to drive a power MOSFET
t directly. And the maximum duty-cycle of LD7522 is limited
to 75% to avoid the transformer saturation.
Fig. 19

Oscillator and Switching Frequency

Startup Current and Startup Circuit The switching frequency of LD7522 is fixed as 65KHz
internally to provide the optimized operations by considering
The typical startup circuit to generate the LD7522 is shown
the EMI performance, thermal treatment, component sizes
in Fig. 20. During the startup transient, the Vcc is lower
and transformer design.
than the UVLO threshold thus there is no gate pulse
produced from LD7522 to drive power MOSFET.
Therefore, the current through R1 will provide the startup Voltage Feedback Loop
current and to charge the capacitor C1. Whenever the Vcc The voltage feedback signal is provided from the TL431 in
voltage is high enough to turn on the LD7522 and further to the secondary side through the photo-coupler to the COMP

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pin of LD7522. The input stage of LD7522, like the A 350nS leading-edge blanking (LEB) time is included in the
UC384X, is with 2 diodes voltage offset then feeding into the input of CS pin to prevent the false-trigger from the current
voltage divider with 1/3 ratio, that is, spike. However, the total pulse width of the turn-on spike is
1 decided by the output power, circuit design and PCB layout.
V+ (PWM COMPARATOR ) = × ( VCOMP − 2VF )
3 It is strongly recommended to adopt a smaller R-C filter (as
shown in figure 21) to avoid the CS pin being damaged by
A pull-high resistor is embedded internally thus can be
the negative turn-on spike.
eliminated on the external circuit.

Dual-Oscillator Green-Mode Operation

There are many different topologies has been implemented
in different chips for the green-mode or power saving
requirements such as “burst-mode control”, “skipping-cycle
mode”, “variable off-time control “…etc. The basic operation
theory of all these approaches intended to reduce the
switching cycles under light-load or no-load condition either
by skipping some switching pulses or reduce the switching
frequency.

By using this dual-oscillator control, the green-mode

frequency can be well controlled and further to avoid the
generation of audible noise.

Internal Slope Compensation

A fundamental issue of current mode control is the stability
problem when its duty-cycle is operated more than 50%. To Fig. 21
stabilize the control loop, the slope compensation is needed
in the traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In LD7522,
Brownout Protection & Line Compensation
the internal slope compensation circuit has been BNO pin plays 2 different roles in LD7522. The major

implemented to simplify the external circuit design. function is to set the brownout protection point, and at the
same time, it also provides the line compensation function
like in LD7520.
Current Sensing, Leading-edge Blanking Since the voltage on the BNO pin is proportional to the bulk
capacitor voltage thus represented the line voltage. A
The typical current mode PWM controller feedbacks both
brownout comparator is implemented to detect the abnormal
current signal and voltage signal to close the control loop
line condition then shutdown the controller to prevent the
and achieve regulation. The LD7522 detects the primary
damage. Figure 22 shows the operation. When VBNO is
MOSFET current from the CS pin, which is not only for the
lower than 1.25V, the gate output will be kept off even the
peak current mode control but also for the pulse-by-pulse
Vcc already achieves UVLO(on), therefore the Vcc will be
current limit. The maximum voltage threshold of the current
hiccup between UVLO(on) and UVLO(off). Until the line
sensing pin is set as 0.85V. Thus the MOSFET peak current
voltage is higher enough so that VBNO is higher than 1.25V,
can be calculated as:
the gate output will start switching when the next UVLO(on)
(0.85 − VLINE _ COMPENSATION ) is tripped. A hysteresis is implemented to prevent the false
IPEAK(MAX) =
RS trigger during turn-on and turn-off.

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On the other hand, LD7522 detects the voltage on the BNO
pin to feed the line compensation signal on the current
sense circuit. Figure 23 shows the circuit. Thanks to this
implementation, the OCP level of high-line and low-line can
be achieve to very closed point.
The voltage gain from the BNO voltage to line compensation
is 0.04 (V/V). The relationship between BNO pin voltage
and the line compensation is illustrated in figure 24.

Line Voltage

Fig. 24
t

Over Load Protection (OLP)

VBNO
To protect the circuit from the damage during over load
condition or short condition, a smart OLP function is
1.25V
1.10V implemented in the LD7522. Figure 25 shows the
AC OK area
waveforms of the OLP operation. Under such fault
condition, the feedback system will force the voltage loop
t
toward the saturation and thus pull the voltage on COMP pin
Vcc
(VCOMP) to high. Whenever the VCOMP trips the OLP

UVLO(on)
threshold 5.0V and keeps longer than 30mS, the protection
UVLO(off) is activated and then turns off the gate output to stop the
switching of power circuit. The 30mS delay time is to
t
prevent the false trigger from the power-on and turn-off
OUT
transient.

Non-
Non-Switching Switching
Switching

Fig. 22

2 ⋅ Vac

Fig. 23
Fig. 25

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By using such protection mechanism, the average input
power can be reduced to very low level so that the
component temperature and stress can be controlled within V (OVP ) = 2.5V ⋅ (1 +
R2
)
R1
the safe operating area.

Over Voltage Protection (OVP)

The Vgs ratings of the nowadays power MOSFETs are most
with maximum 30V. To prevent the component damage
from the fault condition, LD7522 is implemented the
protection through the OVP pin. Figure 26 and figure 27
show 2 different configurations to programming the OVP
setting point --- zener detection and voltage divider. Figure Fig. 27
26 provided zero bias current under normal operation so
that it will not affect the startup timing. But the tolerance of
OVP trip point will be higher due to the distribution of the
breakdown voltage of zener diode.
On the other hand, the circuit of figure 27 will get the
benefits on the cost and that OVP accuracy but the value of
R1 and R2 must be very high to avoid affecting the startup
timing by the load effect.
As shown in figure 28, whenever the voltage on the OVP pin
is higher than the threshold voltage 2.5V, the output gate
drive circuit will be shutdown simultaneous thus to stop the
switching of the power MOSFET. Whenever the voltage
on the OVP pin gets back to lower than 2.5V, the output is
automatically returned to the normal operation on the next
UVLO(on) level.
Fig. 28

Vbulk-cap
(-)LATCH Pin and Over Temperature
V(OVP)= Vz+2.5V Protection (OTP) --- Latched Mode Protection
Under some abnormal conditions, the ambient temperature
Vz
may be increased significantly and causes some damage on
VCC
the components or further inhibits the dangerous. To
OVP prevent the power circuit damage from the system abnormal,
LD7522
the OTP is required. The OTP circuit is implemented by
sensing the hot-spot of power circuit like power MOSFET or
GND output rectifier. It can be easily achieved by connect a
NTC on the (-)LATCH pin of LD7522. When the device
Fig. 26 temperature or ambient temperature rises high, the
resistance of NTC will be decreased so that the voltage on
the (-)LATCH pin will be
V( − )LATCH = 100μA × RNTC

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 LD7522
When the V(-)LATCH is lower than the threshold voltage
(typical 2.5V), LD7522 will shutdown the gate output and
then latch-off the power supply. On LD7522, the controller
Summary of Protections
will be kept latched until the Vcc drop lower than 8V (power There are several ways to control the on/off of LD7522. The

down reset) and the fault condition is removed. That details are listed as the table below.

means the gate output is still off even the abnormal

condition is released. The only way to successfully re-start Turn Off Operation
the circuit needs to meet 2 conditions. One is to cool down Comp Pin < Cycle by Cycle Mode
COMP
the circuit thus NTC resistance is increased then V(-)LATCH is 1.4V Non-latch
higher than 3.5V. Another condition is to remove the AC Comp Pin >
OLP
power cord and begin another AC power-on recycling. The 5.0V
detail operation is depicted as figure 29. OVP Pin > Hiccup Mode
OVP
2.5 V Non-latch
BNO Pin < Re-start after next UVLO(on)
Brownout 1.25V with
Hysteresis
(-)LATCH Pin Latch Mode
OTP
< 2.5V
Table 1

Fig. 29

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Package Information

SOP-8

Dimensions in Millimeters Dimensions in Inch

Symbols
MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.229 0.007 0.009

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

θ 0° 8° 0° 8°

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Package Information
DIP-8

Dimension in Millimeters Dimensions in Inches

Symbol
Min Max Min Max

A 9.017 10.160 0.355 0.400

B 6.096 7.112 0.240 0.280

C ----- 5.334 ------ 0.210

D 0.356 0.584 0.014 0.023

E 1.143 1.778 0.045 0.070

F 2.337 2.743 0.092 0.108

I 2.921 3.556 0.115 0.140

J 7.366 8.255 0.29 0.325

L 0.381 ------ 0.015 --------

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should

verify the datasheets are current and complete before placing order.

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Revision History

Rev. Date Change Notice

00 4/4/06 Original Specification.

01 8/31/06 Revision: Latch protection turn-on trip level, OVP trip level, and De-latch Vcc level

Add: Application circuit & BOM list

02 12/8/2006 Revision: Block Diagram

03 1/16/2008 Green Package Option

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