Overview
Create Micro-Architecture and Software Specification (MASS) Document designed through our methodology that would enable developers or enthusiasts to modify Rocket-Chip’s modules and create an Intellectual Property (IP) using it.
Software Methodology
- Object Oriented Programming (OOP) principles and high-level Functional Programming concepts were used to better understand the structure of the Rocket-Chip code.
- Flowcharts, UML Class Diagrams and Block Diagrams were made to understand the in-depth functionality of each module inside the Rocket-Chip.
Complexity of Task
- Rocket-Chip contains 328 source files of Scala in 23 directories, and 33,427 total lines of Scala code.
- To the best of our knowledge there is no previous MASS Document of Rocket-Chip available for micro-architecture as well as software level understanding.
Future Research
- Integrate peripherals with the Rocket-Chip SoC that are not available in the Rocket-Chip repository which includes GPIO, I2C, JTAG etc.
- Creates parameterizable Micro-Architecture.
- Extend to include the any Extensions.
Team Members
| Muhammad Uzair Qureshi(Team Lead) | BE (Computer Systems) | Batch 2018 |
| Talha Ahmed | BS (Software Engineering) | Batch 2018 |
| Syeda Fizza Jaffery | BS (Software Engineering) | Batch 2018 |
| Almas Ibrahim | BS (Software Engineering) | Batch 2018 |
| Muhammad Mohsin Siddiqui | BS (Software Engineering) | Batch 2018 |
| Mohammad Shahzaib | BS (Software Engineering) | Batch 2018 |
| Shahzaib Kashif | BS (Software Engineering) | Batch 2018 |
Team Mentors
| Engr. Farhan Ahmed | Senior Lecturer, UIT |
Ibtida System on a Chip
Ibtida - ابتدا means "The Beginning", this System on a Chip (SoC) is the start of many RISC-V based SoCs to come. It is the first CHISEL-based chip to be taped out from Pakistan, and has been designed by Muhammad Hadir Khan, Sajjad Ahmed, and Usman Zain; engineering graduate and undergraduate students respectively. The physical layout of the design is achieved by Aireen Amir Jalal, who is also an engineering graduate. Ibtida is a simple SoC, with GPIO as a peripheral, external instruction and data memories, connected with the TileLink interconnect. It is built around RISC-V based 5 stage pipelined core Buraq-Mini, all developed from scratch using CHISEL HCL.
FEATURES:
- RV32IM extension support.
- 5 stage pipelined core.
- Separate instruction and data memories (each 256 Bytes).
- TileLink Un-Cached Lightweight (TL-UL) Bus Protocol.
- GPIO peripheral with 30 I/Os connected to the I/O pads.
Team Members
| Aireen Amir Jalal | BE (Electrical Engineering) | Batch 2020 |
| Sajjad Ahmed | BE (Computer Systems) | Batch 2017 |
| Usman Zain ul Abiden | BS (Computer Science) | Batch 2017 |
| Hadir Khan | BE (Computer Systems) | Batch 2015 |
Team Mentor
| Dr. Ali Ahmed | Assistant Professor, UIT |
Ghazi System on a Chip
An SoC (System on a Chip) design for Google sponsored Open MPW shuttles for SKY130. The processor core is the 3-stage version of the Buraq Core RV32IMC. The hardware implementation incorporates options such as IRQ, Multiply, Divide and the compressed (16 bit) ISA for embedded applications. The SoC has peripherals such as GPIO, UART, a platform level interrupt controller (PLIC) as well as a timer and a debug module all connected using the Tilelink Interconnect and is going to be fabricated using a 130nm process in collaboration with Efabless and SkyWater which will be funded by Google
FEATURES:
- Support for M extension with a single cycle "Fast" multiplier
- Separate instruction and data memories
- TileLink Un-Cached Lightweight (TL-UL) Bus Protocol
- 32 GPIO with configurable interrupts and option for masked writing
- 2 pin full duplex UART • RISC-V compliant interrupt controller
- 64-bit timer with 12-bit prescaler and 8-bit step register
- JTAG Test Access Port (TAP) for debug
Team Members
| Hamza Shabbir | BE (Electrical Engineering) | Batch 2019 |
| Wajeh ul Hasan | BE (Electrical Engineering) | Batch 2019 |
| Zain Rizwan Khan | BE (Computer Systems) | Batch 2014 |
| Zeeshan Rafique | BE (Computer Systems) | Batch 2017 |
Team Mentor
| Dr. Ali Ahmed | Assistant Professor, UIT |
Burq IDE
BURQ (برق) IDE is a RISCV core simulator. It simulates the working and testing of any 32, 64-bit RISC V core on I, M, C and V extension support. The idea is that a core (either written in chisel or Verilog) could be tested via the ide automatically without setting up custom compilers or setting paths to the text file and writing scripts, making the entire process automated. Furthermore essential features of the ide like error correction find and replace and more are added for ease of use for the end-user. It supports regression testing for RISC V processors so that the user can verify if their core is working optimally.
Team Mentor
| Engr. Farhan Ahmed | Senior Lecturer, UIT |