Stars
A free, open source, and extensible speech-to-text application that works completely offline.
A SystemVerilog language server based on the Slang library.
A Python package for creating and solving constrained randomization problems.
HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.
My own Prompts for Custom instructions ChatGPT
Verilog VPI module to dump FST (Fast Signal Trace) databases
A Hardware Description Language based on the Rust Programming Language
Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
A debugging and profiling tool that can trace and visualize python code execution
🇯 JSON encoder and decoder in pure SystemVerilog
An example of asciidoc rendered on github (.adoc)
A dependency management tool for hardware projects.
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
Explain complex systems using visuals and simple terms. Help you prepare for system design interviews.
CLI platform to experiment with codegen. Precursor to: https://lovable.dev
version-string management for VCS-controlled trees
Share, discover, and collect prompts from the community. Free and open source — self-host for your organization with complete privacy.
A List of Free and Open Source Hardware Verification Tools and Frameworks