Thanks to visit codestin.com
Credit goes to GitHub.com

Skip to content
View shtzw965's full-sized avatar
🐭
🐭

Block or report shtzw965

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

EDK II

C 5,742 3,010 Updated Jan 26, 2026

Mirror of git.qemu.org/seabios.git

C 72 40 Updated Jan 20, 2026

The source for the Linux kernel used in Windows Subsystem for Linux 2 (WSL2)

C 10,074 1,360 Updated Dec 1, 2025

All Algorithms implemented in Python

Python 217,181 49,993 Updated Jan 25, 2026
Go 931 123 Updated Jan 12, 2026

Windows paravirtualized drivers for QEMU\KVM

C 2,543 437 Updated Jan 26, 2026

An unidentifiable mechanism that helps you bypass GFW.

C++ 19,618 3,054 Updated Aug 21, 2024

A platform for building proxies to bypass network restrictions.

Go 46,895 8,899 Updated Oct 6, 2025

Hysteria is a powerful, lightning fast and censorship resistant proxy.

Go 18,568 1,997 Updated Jan 12, 2026

The Python programming language

Python 71,230 33,960 Updated Jan 26, 2026
Verilog 219 47 Updated Jun 25, 2025

SystemRDL 2.0 language compiler front-end

C++ 270 76 Updated Jan 16, 2026

Synopsys License patcher

37 17 Updated Sep 12, 2024

数字IC相关资料

1,357 354 Updated Jul 1, 2025

The Tcl Core. (Mirror of core.tcl-lang.org)

C 767 202 Updated Jan 26, 2026

An AXI4-based SRAM Controller

SystemVerilog 6 1 Updated Dec 14, 2024

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

Scala 21 3 Updated May 12, 2025

An AXI4-based VGA Controller

SystemVerilog 3 1 Updated Dec 14, 2024
Verilog 5 3 Updated Jun 21, 2019

AXI4 VIP for Reg Verifiation

SystemVerilog 4 7 Updated Apr 29, 2024

Open-source high performance AXI4-based HyperRAM memory controller

Verilog 82 19 Updated Oct 6, 2022

AXI总线连接器

SystemVerilog 105 25 Updated Mar 26, 2020

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL 148 24 Updated Jan 7, 2026

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,472 333 Updated Dec 9, 2025

The Ultra-Low Power RISC-V Core

Verilog 1,713 406 Updated Aug 6, 2025

Random instruction generator for RISC-V processor verification

Python 1,246 371 Updated Oct 1, 2025

RISC-V Instruction Set Manual

TeX 4,463 786 Updated Jan 25, 2026

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,400 771 Updated Jan 26, 2026

ASIC Design kit for Skywater 130 for use with mflowgen

Verilog 14 6 Updated Mar 12, 2023
Next