BBC Micro Model B/Master core
This is a port of Mike Sterlings great BBC Micro on FPGA with major changes by Stephen Leary, David Banks and others.
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BBC Micro Model B/Master core
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- VHDL 48.4%
- Verilog 36.7%
- Tcl 6.2%
- C++ 4.3%
- SystemVerilog 4.0%
- Makefile 0.4%