Open source ARM Cortex-M microcontroller library

An ethernet_switch prj for FPGA. Based on xilinx artix-7 FPGA.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A Python wrapper for libhackrf

A Python wrapper for libhackrf

Dataset with IQ signals captured from multiple Sub-GHz technologies (Sigfox, LoRA, IEEE 802.15.4g, IEEE 802.15.4 SUN-OFDM, IEEE 802.11ah)

Search for award inventory using Node.js and Headless Chrome!

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

An alternative to the immich-CLI command that doesn't depend on nodejs installation. It tries its best for importing google photos takeout archives.

A tool to populate missing `DateTimeOriginal` EXIF metadata in Google Photos takeout, using Google's JSON metadata.

This is the code that was used for the blog

Small footprint and configurable Ethernet core

Implementation of simple Ethernet MAC for LAN8720 PHY

Harness Open Source is an end-to-end developer platform with Source Control Management, CI/CD Pipelines, Hosted Developer Environments, and Artifact Registries.

This is my personal template collection. Here you'll find templates, and configurations for various tools, and technologies.

Guide by Example

AXI interface modules for Cocotb

Bluetooth PHY based on one-bit input and output

All Digital Radio Platform written in nmigen targeting FPGAs (for now)

nextpnr portable FPGA place and route tool

Verilog Ethernet components for FPGA implementation

Scapy: the Python-based interactive packet manipulation program & library.

A collection of useful .gitignore templates

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Xilinx Embedded Software (embeddedsw) Development

How to set up Xilinx Vivado for source control