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1. Nasdaq-HFT-FPGA Nasdaq-HFT-FPGA Public

   RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

   C 66 25

2. AES AES Public

   RTL implementaion of 128 bit Advanced Encryption Standard (AES) encyption algorithm

   C 10 1

3. ethernet-physical-layer ethernet-physical-layer Public

   RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

   Tcl 32 11

4. Systolic_MAC_with_DFT Systolic_MAC_with_DFT Public

   GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure

   Verilog 28

5. blake2_asic blake2_asic Public

   SKY130A implementatoin of the Blake2s hash algorithm

   Verilog 2