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1. RISC-V-TAPEOUT RISC-V-TAPEOUT Public

   This repository documents my journey in the 20-week RISC-V SoC Tapeout Program by VSD & IIT Gandhinagar. It includes setup proofs, tool installations (Yosys, Icarus Verilog, GTKWave), and system co…

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2. RTL-Design-And-Synthesis-using-Sky130 RTL-Design-And-Synthesis-using-Sky130 Public

   Verilog

3. RISC-V-TAPEOUT-Week-3 RISC-V-TAPEOUT-Week-3 Public

4. RISC-V-TAPEOUT-Week-4 RISC-V-TAPEOUT-Week-4 Public

5. RISC-V-TAPEOUT-Week-5 RISC-V-TAPEOUT-Week-5 Public

6. RISC-V-TAPEOUT-Week-6 RISC-V-TAPEOUT-Week-6 Public