Thanks to visit codestin.com
Credit goes to Github.com

Skip to content
View JANADINI's full-sized avatar

Block or report JANADINI

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. RISC-V-TAPEOUT RISC-V-TAPEOUT Public

    This repository documents my journey in the 20-week RISC-V SoC Tapeout Program by VSD & IIT Gandhinagar. It includes setup proofs, tool installations (Yosys, Icarus Verilog, GTKWave), and system co…

    1

  2. RTL-Design-And-Synthesis-using-Sky130 RTL-Design-And-Synthesis-using-Sky130 Public

    Verilog

  3. RISC-V-TAPEOUT-Week-3 RISC-V-TAPEOUT-Week-3 Public

  4. RISC-V-TAPEOUT-Week-4 RISC-V-TAPEOUT-Week-4 Public

  5. RISC-V-TAPEOUT-Week-5 RISC-V-TAPEOUT-Week-5 Public

  6. RISC-V-TAPEOUT-Week-6 RISC-V-TAPEOUT-Week-6 Public