RISC-V RV64GC emulator designed for RTL co-simulation

AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

Unofficial description of the CUDA assembly (SASS) instruction sets.

The original high performance and small footprint system-on-chip based on Migen™

使用ESP32开发板模拟WIFI MAC地址，实现任意地点钉钉WIFI打卡

esp32修改蓝牙mac地址 模拟蓝牙打卡机

Linux capable RISC-V SoC designed to be readable and useful.

XTRX LiteX/LitePCIe based design for Julia Computing

TinyMaix is a tiny inference library for microcontrollers (TinyML).

Small footprint and configurable PCIe core

VUnit is a unit testing framework for VHDL/SystemVerilog

Build your hardware, easily!

Instruction set simulator for RISC-V, MIPS and ARM-v6m

SERV - The SErial RISC-V CPU

OpenXuantie - OpenC906 Core

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Wrappers for open source FPU hardware implementations.

An energy-efficient RISC-V floating-point compute cluster.

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

A simple superscalar out-of-order RISC-V microprocessor

Source files for SiFive's Freedom platforms

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

A Risc-V implementation in Chisel

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

A 32-bit RISC-V processor for mriscv project

RISC-V Nox core

An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.

RISC-V microcontroller for embedded and FPGA applications