Design and Verification of a Synchronous 8bit-16location FIFO using System Verilog concepts.

A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.

A Sine, Square wave Function Generator utilising Schmitt Trigger and Wein Bridge Oscillator designed on PCB using EasyEDA.

A two player digital chess clock controller used to keep track of time in hrs:mins:sec taken by each player while making their respective move during the passage of the game.

A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.

This project is an attempt to develop hardware solutions to enhance the security of semiconductor memories. As part of this, we implement an Analog Hardware Trojan (a type of hardware attack) to st…

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

A Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).

Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.

Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.