AI-Driven Verilator Gap Checker (langgraph-based)

Intelligent automation and multi-agent orchestration for Claude Code

Enables access from cocotb/Pyuvm to SystemVerilog Verification IP. Besides re-usable code, this repo contains a simple example implementation

Functional verification project for the CORE-V family of RISC-V cores.

A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

Complete UVM TestBench For Verification Of D Flip Flop

A complete UVM TB for verification of single port 64KB RAM

Functional verification project for the CORE-V family of RISC-V cores.

PlanV CI System for testing Verilator-Features

Verilator open-source SystemVerilog simulator and lint system

Verilator open-source SystemVerilog simulator and lint system

The UVM written in Python

Toy project to practice SystemC skills