FaceID login module for Linux

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

Dual-issue RV64IM processor for fun & learning

32-bit Superscalar RISC-V CPU

Rocket Chip Generator

GNU toolchain for RISC-V, including GCC

Send video/audio over HDMI on an FPGA

A Pac-Man Arcade implementation for the TangNano9K using HDMI

SpinalHDL Hardware Math Library

Modular hardware build system

RTL code for Dual-issue microcontroller (Verilog)