Welcome to my journey through the RISC-V SoC Tapeout program VSD!!! 🥰🥰

In this program, we learn to design a System-on-Chip (SoC) from basic RTL to GDSII using open-source tools. Part of India's largest collaborative RISC-V Chip Tapeout initiative, empowering more than 3500 participants to build silicon & advance the nation's semiconductor ecosystem.

1. Successfully installed & verified open-source EDA tools ecosystem
2. Learnt about basic environment setup for RTL design & synthesis
3. Prepared for upcoming RTL ➡️ GSIII flow projects

1. Understood RTL design flow and Verilog-to-hardware synthesis.
2. Learned the role of timing libraries (.lib) in defining delays and constraints.
3. Explored optimization methods for area, power, and speed.
4. Differentiated blocking vs non-blocking assignments.
5. Gained experience with Gate Level Simulation and post-synthesis verification.

1. Understood the basic architecture and components of a System-on-Chip (SoC).
2. Learned how different modules like CPU, memory, and peripherals interact within an SoC.
3. Explored functional modeling techniques to simulate and verify SoC behavior before implementation.
4. Gained insights into bus architectures, data flow, and interconnect design.
5. Understood the importance of modular design and integration in building scalable SoC systems.

1. Understood the purpose and workflow of Gate Level Simulation (GLS) for verifying post-synthesis functionality and timing.
2. Learned the basics of Static Timing Analysis (STA) and how it ensures the design meets setup and hold time requirements.
3. Explored timing paths, constraints, and slack analysis for timing closure.
4. Gained skills in identifying and debugging timing violations.
5. Understood the importance of GLS and STA in achieving reliable, timing-accurate digital designs.

1. Understood NMOS I–V characteristics and how current varies across different operating regions.
2. Learned about velocity saturation and its influence on short-channel transistor behavior.
3. Determined CMOS inverter switching threshold and analyzed dynamic performance through transient simulations.
4. Evaluated noise margins to assess CMOS inverter robustness and reliability.
5. Studied the impact of power supply and device variations on overall circuit stability and performance.

1. Floorplanning defines the chip’s physical structure — setting die/core areas, placing macros and I/O pads, and organizing standard cell rows while ensuring good power delivery through PDN design.
2. Placement arranges standard cells within the floorplan to minimize wire length, reduce congestion, and meet timing constraints, using both global (approximate) and detailed (final) placement stages.
3. Successful physical design balances logical connectivity, power integrity, and physical layout efficiency to ensure optimal chip performance and manufacturability.

I am grateful to Kunal Ghosh and Team VLSI System Design (VSD) for the opportunity to participate in the ongoing RISC-V SoC Tapeout Program.