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SystemVerilog design and UVM verification environment for an 8-bit asynchronous FIFO, focusing on robust clock domain crossing (CDC) handling and comprehensive verification.
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Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.
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This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…
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