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Releases: chipsalliance/chisel

Chisel v7.6.0

20 Dec 22:11

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Features

Backend Code Generation

  • Fix name prefixing from views on rhs of connection (by @jackkoenig in #5117)
    Previously views when used on the LHS of a connection operator, views would provide the prefix view_. Now, at least for 1-1 views, the prefix is derived from the name of the target of the view. This is a common issue when using FlatIO.

Fixes

Dependency Updates

Build and Internal Changes

Full Changelog: v7.5.0...v7.6.0

Chisel v7.5.0

09 Dec 19:27
25d2f7b

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API Deprecation

Fixes

  • Support simple views in domain association (by @jackkoenig in #5106)
    Also give a useful error message for non-simple views.
  • Fix boring taps of views of ExtModule ports (by @jackkoenig in #5110)
    This is a common issue when using FlatIO with ExtModules.
  • Support absolute path source locators (by @jackkoenig in #5111)
    The default behavior of Scala-cli is to use a Bloop server running in the root directory for compilation. This results in absolute paths in for source locators at compile time, but our logic had assumed we always had relative paths and was manually stripping the leading forward slash in source locator paths. Instead, we strip the leading forward slash for relative paths by including it in the path prefix we remove, and then in error reporting we add support for paths that are already absolute.

Documentation

Dependency Updates

Build and Internal Changes

  • [main] Enable MiMa for v7.4.0 (by @chiselbot in #5091)
  • Remove all panama related stuff (by @jackkoenig in #5104)
    Remove all Panama-related code. Refresh lit-based tests and put them in CI.
  • Simplify cross build (by @jackkoenig in #5098)
    You now run mill cross builds with just major version, e.g. mill chisel[2.13].compile and mill chisel[3].compile rather than mill chisel[2.13.18].compile and mill chisel[3.3.4].compile.

Full Changelog: v7.4.0...v7.5.0

Chisel v7.4.0

26 Nov 17:05
40942a3

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API Modification

Fixes

Documentation

  • [chisel3.simulator.scalatest.Cli] fixing EmitVpd option description (by @nibrunieAtSi5 in #5072)

Dependency Updates

Build and Internal Changes

  • [main] Enable MiMa for v7.3.0 (by @chiselbot in #5068)
  • Add missing implies for BitsIntf (by @adkian-sifive in #5055)
    Add implies support to Scala 3 Bits
  • Bump to mill 1.0.6 (by @jackkoenig in #5079)
  • [Scala3] Add missing PrintfIntf implementation (by @adkian-sifive in #5086)
    Add missing Scala3 PrintfIntf implementation
  • [Scala3] Support multiple parameter lists for Bundles (by @adkian-sifive in #5085)
    Support multiple parameter lists in Bundles
  • [Scala3] Add support for Selectable Modules (by @adkian-sifive in #5087)
    Make Modules Selectable in Scala 3

Full Changelog: v7.3.0...v7.4.0

Chisel v7.3.0

29 Oct 22:14
42f1a1e

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Features

Backend Code Generation

  • Empty prefixes should be ignored in emission (by @jackkoenig in #5057)
    Previously they would result in an extra '_' in the same of the signal.

Fixes

Documentation

  • [website] Update all website dependencies (by @jackkoenig in #5064)
  • [ci] Update all github actions (by @jackkoenig in #5066)
    Caching has been broken for ages, this should fix that. It also updates all actions to Node 24 released versions if they exist yet. Everything must be moved to Node 25 by April [1].
  • [website] Fix Snapshot API docs by hosting locally (by @jackkoenig in #5067)
    Previously, we linked to s01.sonatype which allowed rendering doc jars in the browser. As Sonatype has been sunset and Maven Central does not appear to support this, we will have to host the latest snapshot ourselves.

Dependency Updates

  • [cd] Bump CIRCT from firtool-1.133.0 to firtool-1.134.0 (by @chiselbot in #5058)
  • [cd] Bump CIRCT from firtool-1.134.0 to firtool-1.135.0 (by @chiselbot in #5063)

Build and Internal Changes

Full Changelog: v7.2.0...v7.3.0

Chisel v7.2.0

17 Oct 17:52
767b9eb

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Features

  • [svsim] Add -j, --build-jobs, and --verilate-jobs (by @seldridge in #5051)
  • ChiselEnum convenience functions; support string interaction (by @maartenboersma in #5036)
    Convenience functions to interact between ChiselEnum and String. Allows RTL readability improvements, especially if Enum values are not yet known at compile time (e.g. decode tables in separate files)
  • Make BitPat accept ChiselEnum (by @maartenboersma in #5046)
    BitPat now accept ChiselEnum as an input.
  • Add option to suppress emission of source locators (by @jackkoenig in #5053)
    Users can now pass --no-source-info to suppress emission of source locators in emitted .fir.

API Deprecation

  • Add HasSerializationOverrides (by @jackkoenig in #5044)
    This is a deprecated API in firrtl.annotations that is similar to HasSerializationHints but allows for overriding the serialization class like OverrideSerializationClass does for Annotations themselves.
    Also remove the Annotation self typing on OverrideSerializationClass because it is pointless.

Fixes

  • [svsim] Fix bugs in generated simulation code for Verilator backend. (by @xiaoh105 in #5054)
    Fix the run_simulation API in resource file simulation-driver.cpp for verilator backend to allow delayed events from BlackBox be scheduled by Verilator properly.

Dependency Updates

  • [cd] Bump CIRCT from firtool-1.131.0 to firtool-1.132.0 (by @chiselbot in #5034)
  • Bump to Scala 2.13.17 (by @jackkoenig in #5039)
    Note: Scala 2.13.17 has a new warning for inferred structural types as a Scala 3 compatibility issue. This warning applies to the common val io = IO(new Bundle { ... }) pattern in Chisel. It is not actually a problem because Chisel uses Programmatic Structural Types in Scala 3. You can suppress this warning in your build by adding-Wconf:msg=will no longer have a structural type:s to your scalacOptions. See configurable warnings for more details on -Wconf.
  • [cd] Bump CIRCT from firtool-1.132.0 to firtool-1.133.0 (by @chiselbot in #5045)

Build and Internal Changes

  • [main] Enable MiMa for v7.1.1 (by @chiselbot in #5035)
  • [Scala3] Move CIRCT LTL from src/main/scala-2 to src/main/scala/ (by @adkian-sifive in #5047)
  • [Scala3] BundlePhase updates (by @adkian-sifive in #5043)
    BundlePhase now runs after PickleQuotes to sidestep Scala 3 compiler bug scala/scala3#23793
  • [Scala3] Rewrite svsim Verilator backend argument stringification (by @adkian-sifive in #5042)
    Svsim Verilator Backend argument generation was refactored to work with Scala 3
  • [Scala3] Add apply methods to assert, assume, cover (by @adkian-sifive in #5048)
    Added Scala 3 assert, assume, cover apply methods for Scala 3
  • [Scala3] Add BundleSpec and enable Scala3 CI testing (by @adkian-sifive in #5050)
    Enable CI testing in Scala 3 starting with BundleSpec

Full Changelog: v7.1.1...v7.2.0

Chisel v7.1.1

27 Sep 23:50
5cb6aa7

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Fixes

  • Rename private[chisel3] SourceInfo$Intf to SourceInfoIntf (by @jackkoenig in #5033)
    This works around an issue in IntelliJ around using the macro to materialize SourceInfo.

Documentation

Build and Internal Changes

Full Changelog: v7.1.0...v7.1.1

Chisel v7.1.0

22 Sep 22:18
40c1f46

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Features

Fixes

  • Fix construction of PseudoModules to have correct parent (by @jackkoenig in #5012)
    This fixes subtle bugs where accessing children of an Instance (whether directly or by using Select APIs) could change the result of future Select to be incorrect. For example, a call to Select.unsafe.allCurrentInstancesIn could cause Select.unsafe.currentInstancesIn to also incorrectly include grandchildren and all other transitive children.
  • [svsim] Update c++ CFLAGS for verilator from c++14 to c++17 (by @Gallagator in #5017)
    Verilator CFLAGS bumped from c++14 to c++17
  • Overload Stage methods to use Seq[Annotation] (by @jackkoenig in #5030)
    Also deprecate the older forms using AnnotationSeq.

Documentation

  • [docs] Update layer docs for temporal layer, NFC (by @seldridge in #5020)
  • [docs] Fix duplicate versions in Firrtl Version table (by @jackkoenig in #5025)
    Also refactor some build util code to be Tasks so they can be cached on disk.
  • [doc] Document temporal layers and ChiselSim (by @seldridge in #5027)

Dependency Updates

  • [cd] Bump CIRCT from firtool-1.128.0 to firtool-1.129.0 (by @chiselbot in #5010)
  • [cd] Bump CIRCT from firtool-1.129.0 to firtool-1.130.0 (by @chiselbot in #5015)
  • [cd] Bump CIRCT from firtool-1.130.0 to firtool-1.131.0 (by @chiselbot in #5021)

Build and Internal Changes

Full Changelog: v7.0.0...v7.1.0

Chisel v7.0.0

08 Sep 20:45
c1ed928

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Features

  • Preserve UInt and SInt literals across .pad (by @jackkoenig in #4156)
  • Add support for marking things as readOnly (by @jackkoenig in #4190)
    Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
  • Add ChiselStage.emitCHIRRTLFile (by @jackkoenig in #4232)
    Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
  • Make requireTypeEquivalent public and add context message (by @mwachs5 in #4243)
    Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
  • Add map method for Valid (by @tymcauley in #4255)
    Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
  • Add more information when probe types don't match (by @mwachs5 in #4269)
    Add more information to the error message when attempting to probe.define to a mismatched chisel type.
  • Add AffectsChiselName (by @adkian-sifive in #4283)
    Adds new trait AffectsChiselName that adds support for naming user-defined types
  • Add --remap-layers to ChiselStage (by @seldridge in #4322)
  • Add common layers to Chisel (by @seldridge in #4326)
  • Add skipIfAlreadyInBlock arg to layer.block (by @seldridge in #4327)
  • Add skipIfLayersEnabled param to layer.block (by @seldridge in #4346)
  • Add layer.elideBlocks API (by @seldridge in #4348)
  • Make layer.addLayer API public (by @seldridge in #4349)
  • Add Property expression for list concatenation. (by @mikeurbach in #4347)
    This adds a list concatenation operation for Property[Seq[T]], using the same typeclass approach used for other Property expressions.
  • Add support for circt.OutputDirAnnotation. (by @dtzSiFive in #4352)
    Expose capability to request a Module be placed in a specific directory.
    Functions as with Layer output directories.
  • Make '--module' support arguments (by @seldridge in #4358)
  • Add DataMirror API for currentInstancePorts. (by @mikeurbach in #4362)
    This allows users to query an Instance without it being closed or forcing it to close, which can be useful in atModuleBodyEnd and other scenarios.
  • Add experimental Select APIs for current instances in a BaseModule. (by @mikeurbach in #4363)
    This is useful in situations like atModuleBodyEnd to reflect on the current BaseModule before it is closed.
  • Add Path.apply() to support HasTarget (by @debs-sifive in #4364)
    Adds Path.apply() function that support HasTargets, so that the paths of things that extend HasTarget, like SRAM, can be put into properties.
  • feat: implement SerializableModuleElaborator (by @unlsycn in #4409)
    Add SerializableModuleElaborator
  • Add SourceLocator for Sequence (by @unlsycn in #4436)
    Add source locator for Sequence
  • Add Property expression for integer shift left (by @maerhart in #4440)
    This adds an API for integer Property shift left.
  • Support creation of Paths from HasTargets (by @debs-sifive in #4455)
  • Add --firtool-option arg to ChiselStage (by @seldridge in #4463)
  • switch SRAMDescription to Class (by @sequencer in #4437)
  • add additionalAnnotations for SerializableModuleElaborator (by @sequencer in #4477)
  • Implement Lookupable for HasTarget (used by SRAM) (by @jackkoenig in #4481)
  • Allow BoringUtils to use existing port in a closed module (by @tmckay-sifive in #4484)
    When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
  • Implement Lookupable for Unit (by @jackkoenig in #4497)
  • [Module] Add afterModuleBuilt hook (by @fabianschuiki in #4479)
    The new afterModuleBuilt hook can be used to schedule code to be executed once a module has been fully generated and its definition is available. This allows further collateral such as unit tests to be generated alongside a module.
  • Add withModulePrefix (by @mmaloney-sf in #4487)
  • Add AutoBlackbox (by @unlsycn in #4495)
  • Add new InlineInstanceAllowDedup trait (by @rwy7 in #4508)
  • Add module prefixing to BaseModule definitions (by @jackkoenig in #4509)
    • BaseModule.localModulePrefix can be used to set a prefix for the module and its children.
    • BaseModule.localPrefixAppliesToSelf (defaults to true) allows the module to exclude itself from the prefix.
    • localModulePrefix composes with prefixes added via withModulePrefix.
  • feat: add CIRCTSRAMInterface (by @unlsycn in #4494)
    Add CIRCTSRAMInterface
  • Add APIs to omit module prefix separator (by @jackkoenig in #4532)
    • withModulePrefix now optionally takes a 2nd parameter includeSeparator (passing false will omit separator).
    • Overriding localModulePrefixUseSeparator in a Module to false will omit separator for local prefix applied by overriding localModulePrefix in that Module.
  • feat: add SRAMBlackBox (by @unlsycn in #4544)
  • Add partial cross-compilation for Scala 3 (by @adkian-sifive in #4549)
    Adds initial support for Scala 3 LTS version 3.3.3
  • [util] Add a withShadowLayer Queue (by @seldridge in #4589)
  • Add FormalTest marker (by @fabianschuiki in #4635)
  • [core] Add layer block that returns colored wire (by @seldridge in #4623)
  • Add UnitTest marker and test discovery utility (by @fabianschuiki in #4642)
  • [chiselsim] Add Default (non-Ephemeral) Simulator (by @seldridge in #4665)
  • [Chiselsim] Add WithTestingDirectory (by @seldridge in #4669)
  • [chiselsim] Rewrite EphemeralSimulator in terms of DefaultSimulator (by @seldridge in #4675)
  • [chiselsim] Add, use HasSimulator type class (by @seldridge in #4678)
  • [firrtl] Add, use dramaticMessage (by @seldridge in #4684)
  • [chiselsim] Add SimulatorAPI, reduce DefaultSimulator to nothing (by @seldridge in #4680)
  • [chiselsim] Add ChiselSim APIs (by @seldridge in #4685)
  • Add simple API for generating testharnesses inline (by @tmckay-sifive in #4629)
    Add an API to generate testharnesses inline that are emitted as additional public modules in the output.
  • Dev/seldridge/switch to chisel settings (by @seldridge in #4708)
  • Add RequireProperty and EnsureProperty (by @fabianschuiki in #4681)
  • [chiselsim] Add FIRRTL macro control (by @seldridge in #4699)
  • [Chiselsim] Replace Chiselspec w/ ChiselSim (by @seldridge in #4706)
  • [testing] Add FileCheck API (by @seldridge in #4749)
  • Add formal contracts (by @fabianschuiki in #4682)
  • [testing] Add HasTestingDirectory subdir factory (by @seldridge in #4774)
  • [chiselsim] Allow command line options to be passed to ChiselSim tests (by @seldridge in #4773)
  • [scalatest] Add HasCliSimulator (by @seldridge in #4776)
  • Change Data._fromUInt to protected (by @jackkoenig in #4782)
    This enables external libraries like FixedPoint to override it. This is not an ideal API, but it works until we have a better way to do this.
  • [chiselsim] Add ControlAPI w/ Waveform Enable/Disable Support (by @seldridge in #4779)
  • [ChiselSim] Factor reset procedure out of SimulatorAPI and into stimulus (by @seldridge in #4784)
    -...
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Chisel v7.0.0-RC4

29 Aug 17:53
c1ed928

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Chisel v7.0.0-RC4 Pre-release
Pre-release

Features

  • Add PopCount compare functions to reduce circuitry for common cases (by @maartenboersma in #5002)
    Can call PopCount.greaterThan(n), PopCount.equalTo(n), PopCount.atLeast(n). If n is such that it allows for optimization, the generated circuitry is cheaper and faster compared to "first PopCount, then compare".

API Modification

  • Make ChiselEnum width inference consider known-width Value() literals (by @CSharperMantle in #4990)
    The inferred width for a ChiselEnum using Value() now correctly accommodates both known-width values and the largest specified literal integer. Closes #4989.

Backend Code Generation

  • Support emitting variadic cat (by @jackkoenig in #4992)
    This should not be visible to most users unless they inspect emitted .fir. It reduces memory use, improves performance, and reduces the size of emitted .fir a little bit, ~2-5% depending on the design.
  • Bump emitted FIRRTL version to 6.0.0 (by @jackkoenig in #5008)

Fixes

Dependency Updates

  • [cd] Bump CIRCT from firtool-1.125.0 to firtool-1.126.0 (by @chiselbot in #4991)
  • [cd] Bump CIRCT from firtool-1.126.0 to firtool-1.127.0 (by @chiselbot in #4998)
  • [cd] Bump CIRCT from firtool-1.127.0 to firtool-1.128.0 (by @chiselbot in #5007)

Build and Internal Changes

Full Changelog: v7.0.0-RC3...v7.0.0-RC4

Chisel v7.0.0-RC3

11 Jul 23:01
1a2980c

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Chisel v7.0.0-RC3 Pre-release
Pre-release

Features

Dependency Updates

  • [cd] Bump CIRCT from firtool-1.124.0 to firtool-1.125.0 (by @chiselbot in #4973)
  • [cd] Bump CIRCT from firtool-1.124.0 to firtool-1.125.0 (by @chiselbot in #4974)

Build and Internal Changes

  • [Scala3] Split plugin resource files based on Scala major version (by @adkian-sifive in #4971)
    Split plugin resource files into separate directories for Scala 2 and Scala 3
  • [Scala3] Add Bundle plugin (by @adkian-sifive in #4947)
    Adds Bundle plugin
  • Upgrade to Mill 1.0.0 (by @jackkoenig in #4972)
    No SNAPSHOT publishing yet, that will be follow on work. See the Mill 1.0.0 changelog.

Full Changelog: v7.0.0-RC2...v7.0.0-RC3