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Domain-specific language designed to streamline the development of high-performance GPU/CPU/Accelerators kernels

Python 4,745 403 Updated Jan 18, 2026
SystemVerilog 17 9 Updated Oct 7, 2025

llama3 implementation one matrix multiplication at a time

Jupyter Notebook 15,238 1,289 Updated May 23, 2024

Processing-In-Memory (PIM) Simulator

C++ 219 65 Updated Dec 12, 2024
C++ 48 12 Updated Sep 8, 2022

OpenExSys_NoC a mesh-based network on chip IP.

SystemVerilog 20 Updated Dec 1, 2023

Gvsoc implementation of RedMule

C++ 2 Updated Dec 15, 2023
SystemVerilog 5 Updated May 31, 2023

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

C 483 172 Updated Nov 27, 2025
1 Updated Oct 29, 2021

Python application for creating energy profile diagrams as '.svg' files. Extra analysis for catalytic cycle diagrams.

Python 81 25 Updated May 8, 2021

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

SystemVerilog 228 52 Updated Nov 22, 2023

A 4 stage pipelined 32-bit RISCV core with only 8 base integer registers

Verilog 1 Updated Sep 4, 2021