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Zhengzhou University
- Zhengzhou, China
- https://lauchinyuan.github.io/
- channel/UCgZzwGbKnsISU2mJxxyopVw
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Functional verification project for the CORE-V family of RISC-V cores.
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
Open-source high-performance RISC-V processor
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
《动手学深度学习》:面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
A very simple and easy to understand RISC-V core.
开放原子开源基金会孵化的物联网操作系统,捐赠前为腾讯物联网终端操作系统TencentOS Tiny