This repository is a port of the "RISCOF RISC-V Architecture Test Framework" to test the NEORV32 RISC-V Processor for compatibility to the RISC-V ISA specifications. Currently, the following tests are supported:

• rv32i_m\A - atomic memory operations (Zaamo only)
• rv32i_m\B - bit-manipulation (Zba + Zbb + Zbs)
• rv32i_m\C - compressed instructions (Zca + Zcb)
• rv32i_m\I - base integer ISA
• rv32i_m\K - scalar cryptography, Zkn and Zks (Zbkb + Zbkc + Zbkx + Zknd + Zkne + Zknh + Zksed + Zksh)
• rv32i_m\M - hardware integer multiplication and division
• rv32i_m\Zicond - conditional operations
• rv32i_m\Zifencei - instruction stream synchronization
• rv32i_m\Zimop - may-be-operation
• rv32i_m\hints - hint instructions
• rv32i_m\pmp - physical memory protection (M + U modes)
• rv32i_m\privilege - privileged machine-mode architecture

Several tools and submodules are required to run this port of the architecture test framework. The repository's GitHub Actions workflow takes care of installing all the required packages.

• neorv32 submodule - the device under test (DUT)
• riscv-arch-test submodule - architecture test cases
• RISC-V GCC toolchain - for compiling native rv32 code
• Sail RISC-V - the golden reference model
• RISCOF - the architecture test framework (including riscv-isac and riscv-config)
• GHDL - the awesome VHDL simulator for simulating the DUT
• Python - used as the main scripting language

RISCOF is configured by a config.ini that defines the the plugins to be used: the device-under-test (NEORV32) and the reference model (Sail RISC-V). Each plugin provides target-specific ISA definitions, environment files like linker scripts and low-level code for interaction with the platform, and Python scripts for the target-specific test runs (compiling tests, invoking the DUT simulator and the reference model's executable, etc.).

• device-under-test: plugins/neorv32
• reference model: plugins/sail_cSim

A full test run is triggered by a shell script (run.sh) that returns 0 if all tests were executed successfully or 1 if there were any errors. The exit code of this script is used to determine the overall success of the according GitHub Actions workflow. The CSS-flavored HTML test report is available as GitHib actions artifact.

The specific NEORV32 rvtest_tb.vhd testbench implements a memory subsystem attached to the core's external bus interface. This subsystem provides main memory and environment control mechanisms: