Blender GDSII Importer with PDK Support

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

A playground for post-quantum cryptography (PQC) on embedded systems and edge devices

NIST FIPS 203 (ML-KEM) standard compliant, C++20, fully `constexpr`, header-only library

A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers

A set of different arbiters designed in Verilog/System Verilog.

LEC - Logic Equivalence Checking - Formal Verification

C++ HDL (Hardware Description Language)

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.

VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.

high level VHDL floating point library for synthesis in fpga

VHDL compiler and simulator

❄️ Icestudio collections manager

A plugin to allow Jenkins Steps with Cadence vManager API

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

An open-source static random access memory (SRAM) compiler.

Small SERV-based SoC primarily for OpenMPW tapeout

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

A Python toolbox for building complex digital hardware

The MyHDL development repository

Icarus Verilog

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

A Framework for CI/CD using Jenkins shared library

Functional Coverage Patterns for FIFO

The UVM written in Python