Jun 2025 - Jul 2025 The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low-performance APB buses.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Functional verification project for the CORE-V family of RISC-V cores.

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

OpenTitan: Open source silicon root of trust

A 5-stage pipelined, rv32i core with branch prediction and hazard detection

Documenting the Lattice ECP5 bit-stream format.