AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
Updated
Dec 9, 2025 - SystemVerilog
#
axi4
Here are 20 public repositories matching this topic...
VeeR EH1 core
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
-
Updated
May 29, 2023 - SystemVerilog
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
-
Updated
Dec 29, 2025 - SystemVerilog
Network on Chip Implementation written in SytemVerilog
-
Updated
Aug 27, 2022 - SystemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
-
Updated
Nov 18, 2024 - SystemVerilog
AXI4 and AXI4-Lite interface definitions
-
Updated
Sep 20, 2020 - SystemVerilog
RISCV CPU implementation in SystemVerilog
asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu
-
Updated
Oct 1, 2025 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
-
Updated
Jan 7, 2026 - SystemVerilog
Formal AXI verification properties from the eXpect framework for secure SoC validation
verification eda systemverilog soc formal-verification axi amba hardware-security questa axi4 axi4-lite hardware-design
-
Updated
Oct 28, 2024 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
-
Updated
Nov 20, 2019 - SystemVerilog
Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.
ci verification rtl vcs systemverilog uvm qos arbitration backpressure sva crossbar questa axi4 jerkins uvm-verification hardware-validation
-
Updated
Aug 21, 2025 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog
-
Updated
May 4, 2024 - SystemVerilog
A general purpose AXI4-Full Master IP for PYNQ-Z2 with Jupyter demo.
-
Updated
Nov 26, 2025 - SystemVerilog
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu
-
Updated
Oct 7, 2024 - SystemVerilog
Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.
protocol randomization vip scoreboard systemverilog questasim uvm axi amba sva axi4 functional-coverage uvm-verification constrained-randomization asserti
-
Updated
Jan 8, 2026 - SystemVerilog
Improve this page
Add a description, image, and links to the axi4 topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi4 topic, visit your repo's landing page and select "manage topics."