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blif

Here are 16 public repositories matching this topic...

IamFlea / BLIF-to-truth-table

Parses BLIF (Berkeley Logic Interchange Format) to a truth table which is easier for parsing in Genetic Programming Algorithms

circuits truth-table blif

Updated Sep 6, 2020
Python

mario33881 / notepadpp-blif_sis

macros (templates) and custom language file (syntax highlight) for Notepad++ to develop BLIF files

syntax-highlighting notepad sis macro notepad-plus-plus blif

Updated Mar 27, 2021

mario33881 / sublime-blif_sis

BLIF (SIS' Berkeley Logic Interchange Format) syntax highlighter and autocompleter package for Sublime Text

syntax-highlighting sublime-text sis univr blif

Updated May 15, 2021
Python

mario33881 / blif2graph

Generate graphs from BLIF files

sis blif

Updated Mar 4, 2023
Python

Koyama-Tsubasa / Advanced_Logic_Synthesis

Coursework of NTHU CS613200 Advanced Logic Synthesis

fpga decomposition logic-synthesis technology-mapping blif

Updated Jun 22, 2023
C++

arc6-202021 / lib_componenti_sis

Elaborato SIS di architettura degli elaboratori (anno 2020-2021), ed altri componenti

university-project sis univr elaborato blif

Updated Sep 11, 2023
Python

byuccl / spydrnet-tmr

TMR utilities for the SpyDrNet project

fpga digital transformations verilog hardware-designs transformation netlist computer-aided-design fpgas electronic-design-automation tmr triple-modular-redundancy blif netlists edif spydrnet eblif

Updated Nov 7, 2023
Python

mario33881 / blifparser

A simple BLIF (berkeley logic interchange format) parser

sis blif

Updated Dec 11, 2023
Python

betterSIS

mario33881 / betterSIS

The modern shell for SIS (the circuit simulator and optimizer)

python sis univr blif

Updated Feb 5, 2024
Python

Aledpl5 / Rock-Paper-Scissors-Circuit

Uni project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif finate-state-machine datapath-design

Updated Feb 7, 2024
SystemVerilog

mattiadane / Rock-Paper-Scissors-Circuit

University project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif datapath-design fsm-designer

Updated Feb 19, 2024
SystemVerilog

tbimbato / Morra-Cinese-UniVR

Questo progetto è incentrato sulla realizzazione di un sistema FSMD per il gioco della Morra Cinese. All'interno di questa repository, troverai i codici sorgenti scritti in linguaggio hardware Verilog e SiS (blif), insieme a tutti i moduli .blif relativi alla progettazione a gate level in SiS.

verilog sis univr blif fsmd

Updated May 6, 2024
TeX

siswrapper

mario33881 / siswrapper

SIS (circuit simulator and optimizer) wrapper for Python

python sis univr blif

Updated Nov 10, 2024
Python

Lipen / circuition

💫 Library for managing Boolean circuits in Kotlin

kotlin circuit bench aig blif and-inverter-graph

Updated Mar 24, 2025
Kotlin

ehw-fit / ariths-gen

Generator of arithmetic circuits (multipliers, adders) and approximate circuits

rtl verilog approximate-computing blif

Updated Aug 15, 2025
C

mario33881 / vscode-blif

BLIF (SIS' Berkeley Logic Interchange Format) highlight and autocomplete extension for Visual Studio Code

syntax-highlighting visual-studio autocompletion sis univr blif vscode-blif autocomplete-keywords

Updated Dec 30, 2025
Python

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