Learn how to build our own RV32I(M) core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Staging area for new features of cocotb

RTL data structure

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

End-to-end Microwatt-based SoC with AXI-Lite, Wishbone, and APB buses, fully verified using Cocotb and taken from RTL to GDSII on Sky130 using OpenLane.

This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation performance.

Simple personal tooling for quickly bootstrapping hardware development projects using open-source tools (Verilator, cocotb, TOML-based configuration)

Reusable and scalable verification framework for Deep Neural Network (DNN) accelerators using Pyuvm, Cocotb, and Portable Stimulus Standard (PSS). Supports generic layer-wise verification and automated multi-layer scenario generation.

A custom AI chip to be taped out soon!

100Gbps FPGA UDP Engine on Xilinx Zynq Ultrascale+ MPSoC

A cocotb kernel for Jupyter

Generic testbench for RISC-V CPUs

Cocotb AHB Extension - AHB VIP

A verification library for digital hardware

Python packages providing a library for Verification Stimulus and Coverage

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

Using pipelineC to program the IceBreaker FPGA Board

A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.