Repository gathering basic modules for CDC purpose
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Updated
Dec 31, 2019 - SystemVerilog
Repository gathering basic modules for CDC purpose
A collection of debugging busses developed and presented at zipcpu.com
Audio Signal Processing SoC Project Website
Graph Processing Framework that supports || OpenMP || CAPI
Covers the DEEDS training material for electronic Design
This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.
Lightweight adventure game inspired by the classic Pokémon series, adapted to run on the DE2i-150 FPGA board.
It contains 10 assignments based on simulation and testing of hardware codes on BASYS board.
Minimal SoC design for alarm clock
Collection of RTL design projects implemented in VHDL and Verilog, including controllers, FSMs, and FPGA-ready modules.
Tetris in low level programming. Made for Nios II processors.
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