HDL libraries and projects
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Jan 9, 2026 - Verilog
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hdl
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 867 public repositories matching this topic...
PlutoSDR Firmware
linux fpga sdr iio transceiver rf hdl plutosdr adalm-pluto active-learning-module plutosdr-fw plutosdr-firmware
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Dec 12, 2025 - Shell
A modern hardware definition language and toolchain based on Python
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Dec 20, 2025 - Python
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
lidar velodyne-sensor velodyne sensor-data hdl lidar-measurements lidar-data-manipulation lidar-camera-calibration velodyne-hdl-sensors sensor-streaming
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Sep 29, 2021 - C++
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
python toolchain documentation fpga sphinx primitives verilog synthesis lattice hdl xilinx-fpga ice40 artix7 artix vpr kintex7 architecture-definitions verilog-simulator symbiflow verilog-simulations
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Jan 6, 2026 - Jupyter Notebook
Hardware Description Languages
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Jul 14, 2025
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain
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Sep 16, 2025 - Verilog
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
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Nov 17, 2025 - Python
Test suite designed to check compliance with the SystemVerilog standard.
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Jan 9, 2026 - SystemVerilog
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
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Jan 9, 2026 - Dart
This Repository invites freelancer friendly neighbourhood developers to contribute to open source .
nodejs android python open-source arduino django mongodb deep-learning reactjs rest-api flutter hdl hacktoberfest verilog-hdl webdevelopment contributions-welcome cool-stuff hacktoberfest2021
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Oct 17, 2022 - Jupyter Notebook
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl
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Nov 25, 2019 - SystemVerilog
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
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Jan 8, 2022 - Python
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling
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Aug 24, 2025 - Python
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